Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 11 • Date Nov. 2012

Filter Results

Displaying Results 1 - 25 of 35
  • Table of Contents

    Publication Year: 2012 , Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (52 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2012 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (39 KB)  
    Freely Available from IEEE
  • An Ultra Low-Power Dual-Band IR-UWB Transmitter in 130-nm CMOS

    Publication Year: 2012 , Page(s): 701 - 705
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB) |  | HTML iconHTML  

    In this brief, a 0-960-MHz/3.1-5-GHz dual-band ultra low-power impulse-radio ultrawideband transmitter is presented. The pulse transmitter integrated circuit is fabricated using a 130-nm CMOS process with the core die area of 0.1 mm2. At 1-MHz pulse repetition frequency, the power consumption values are measured in the lower and the upper bands as 5.6 and 31 μW, respectively. The lower and the upper band “off-time” power consumptions of the transmitter are 0.36 and 1.7 μW, respectively. The dc-to-radio-frequency conversion efficiencies are 11.1% in the lower band and 4.8% in the upper band. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ultralow Power Injection-Locked GFSK Receiver for Short-Range Wireless Systems

    Publication Year: 2012 , Page(s): 706 - 710
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1046 KB) |  | HTML iconHTML  

    This brief presents a novel CMOS Gaussian frequency-shift keying (GFSK) receiver with an ultralow power consumption, which is based on the injection-locking technique for short-range wireless systems. Additionally, through reducing the oscillation current amplitude of the injection-locked oscillator, the GFSK receiver sensitivity is significantly improved. While comprising a submilliwatt low-noise amplifier, a trifilar transformer splitter, and an injection-locked self-oscillating mixer, the proposed receiver is fabricated using a 90-nm CMOS 1P9M technology. Measurement results indicate a sensitivity of -81 dBm, with a power consumption of 1.8 mW, when a Bluetooth GFSK signal with a data rate of 1 Mb/s is received. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Clock-Harvesting Receiver Using 3G CDMA Signals in the 1900-MHz Band

    Publication Year: 2012 , Page(s): 711 - 715
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1122 KB) |  | HTML iconHTML  

    A clock-harvesting receiver is presented, which extracts a 1.2-kHz clock embedded within the third-generation code-division multiple-access standard for the wake-up of a wireless sensor network. The energy-detection-based receiver was fabricated in 0.13-μm CMOS and designed for low-power heavily duty-cycled operation. In active mode, the receiver has a measured sensitivity of -73 dBm while consuming only 298 μW. The harvested-clock output has 7 μs of root-mean-square jitter at the sensitivity level, which improves with higher received power. In sleep mode, the receiver consumes only 44 pW with a start-up time of 80 μs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization

    Publication Year: 2012 , Page(s): 716 - 720
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1590 KB) |  | HTML iconHTML  

    The deterministic jitter due to the intersymbol interference (ISI) is measured on-chip by fractional oversampling, which can be used to adapt the equalization coefficients of a continuous-time linear equalizer. The effective resolution of the jitter measurement is improved to 0.1 unit interval (UI) by sampling the data input by multiphase sampling clocks spaced by 0.7 UI with the proposed fractional oversampling. The ISI jitter measurement technique with the fractional oversampling has been applied to a 4.2-Gb/s mesochronous serial link and implemented in a 0.13-μm CMOS process to prove the concept. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.9-GHz Fractional-N Digital PLL With Subexponent  \Delta \Sigma TDC and IIR-Based Noise Cancellation

    Publication Year: 2012 , Page(s): 721 - 725
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (830 KB) |  | HTML iconHTML  

    This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent ΔΣ time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent ΔΣ TDC generates adaptively scaled exponent-only information to track the finest resolution that prevents overloading for a given input environment. In addition, IIR-based noise cancellation provides easy filtering of delta-sigma modulator noise without tightened matching constraints. The DPLL fabricated in 0.13- μm CMOS consumes 8.6 mW and shows the subexponent operation and IIR noise cancellation. The measured phase noise of DPLL is - 98 dBc/Hz at 200-kHz offset and -111 dBc/Hz at 3-MHz offset with 500-kHz loop bandwidth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of a 5.5-V Class-D Stage Used in + 30-dBm Outphasing RF PAs in 130- and 65-nm CMOS

    Publication Year: 2012 , Page(s): 726 - 730
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (561 KB) |  | HTML iconHTML  

    This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and + 29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors' best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Continuous Class-E Power Amplifier Modes

    Publication Year: 2012 , Page(s): 731 - 735
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    In this brief, a continuum of novel closed-form solutions is derived for class-E power amplifiers (PAs). It is analytically proven that the class-E zero voltage/zero voltage derivative switching conditions can be satisfied for an arbitrarily selected reactive second harmonic switch impedance (Z2S). The higher order harmonic currents are terminated capacitively. The conventional class-E, class- E/F2, and class-EF2 modes are thus subsets of the continuum. The arbitrary selection of Z2S enables robust waveform engineering for performance optimization in specific applications. Furthermore, the theoretical derivation provides important possibilities for wideband class-E PA synthesis. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS Integrated W-band Passive Imager

    Publication Year: 2012 , Page(s): 736 - 740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1166 KB) |  | HTML iconHTML  

    This brief presents an integrated W-band passive imager, including a low-noise amplifier, a Dicke switch, a detector, a low-pass filter, a programmable-gain amplifier, and a 10-bit 20-MHz pipeline analog-to-digital converter (ADC). With digital outputs, the imager is ready to be interfaced with a digital signal processor to complete its system implementation. The chip is realized in a 65-nm CMOS technology. The measured average noise-equivalent power and responsivity are 32 fW/√{Hz} and 103 MV/W, respectively, which represents a noise-equivalent temperature difference of 1.0 K with 30-ms integration time. The integrated imager occupies a silicon area of 1.17 mm2 and burns 151 mW of power. To the authors' best knowledge, this is the first time that a millimeter-wave passive imager is integrated with an on-chip ADC to generate digital outputs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture

    Publication Year: 2012 , Page(s): 741 - 745
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1452 KB) |  | HTML iconHTML  

    This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications

    Publication Year: 2012 , Page(s): 746 - 750
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1026 KB) |  | HTML iconHTML  

    A compound current cell, with n-type, p-type, and bipolar properties, is proposed in this brief and utilized in a current-steering digital-to-analog converter (DAC) to satisfy the application of rail-to-rail voltage sources. In addition, the DAC with cells also has a high-speed fashion. Therefore, this brief presents a 6-bit CMOS current-steering DAC with cells for both communication and rail-to-rail voltage-source applications. Moreover, the effective output voltage step size is improved by appropriately switching these cells and connecting one of the gain control resisters, resulting in an about 6.4-mV step size in a 1.2-V supply. Furthermore, this DAC was implemented in a standard low-power 90-nm 1P9M CMOS technology with the active area of 0.045 mm2. The measured spurious-free dynamic range is more than 36 dB over the Nyquist frequency at 3 GS/s and the DAC consumes 8.32 mW with a near-Nyquist sinusoidal output at the sampling rate of 3 GS/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ultralow-Power Processing Array for Image Enhancement and Edge Detection

    Publication Year: 2012 , Page(s): 751 - 755
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (795 KB) |  | HTML iconHTML  

    This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be turned into anisotropic by a very simple voltage comparator between neighboring nodes whose output controls the gate of the elementary MOS resistor. Anisotropic diffusion enables image enhancement by removing noise and small local variations while preserving edges. A binary edge image can also be attained by combining the output of the voltage comparators. In addition to these processing capabilities, the simulations have confirmed the robustness of the array against process variations and mismatch. The power consumption extrapolated for VGA-resolution array processing images at 30 fps is 570 μW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A New Quadrature PWM Modulator With Tunable Center Frequency for Digital RF Transmitters

    Publication Year: 2012 , Page(s): 756 - 760
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    State-of-the-art quadrature-type modulators for all-digital radio-frequency (RF) transmitters operate optimally at an RF center frequency (fc) that is a fraction of the modulator switching rate. This is a major limitation if the modulators of this type are to be used in multichannel transmitter systems. In this brief, a novel quadrature modulator based on pulsewidth modulation with controllable in-band distortion is presented, which permits continuous adjustment of fc in digital domain. In addition, distortion generation related to digital upconversion of pulsed baseband signals is studied, and suitable compensation methods are given. The performance of the proposed modulator is compared with those of previously published encoding methods in terms of reconstructed RF signal quality and computational complexity. The evaluation results suggest that significant improvements in signal band distortion can be expected with a computational load suitable for real-time reconfigurable hardware realizations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Model for MOS Diodes With V_{\rm th} Cancellation in RFID Rectifiers

    Publication Year: 2012 , Page(s): 761 - 765
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    A theoretical model for diode-connected MOS transistors with a threshold cancellation technique is developed. The model is based on a detailed analysis of the technique with internal threshold cancellation (ITC) and reveals design insight and performance limitations. Derived design equations illustrate the tradeoff between the voltage drop and the reverse leakage of the diode. Furthermore, a design procedure for the optimization of the power conversion efficiency (PCE) of a bridge rectifier with ITC MOS diodes was developed based on the model. A rectifier was designed and implemented in an austriamicrosystems 0.35-μm CMOS process, and Cadence simulation results of the PCE and the voltage conversion efficiency show good agreement with the model. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generalized Series–Parallel RLC Synthesis Without Minimization for Biquadratic Impedances

    Publication Year: 2012 , Page(s): 766 - 770
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    This brief is concerned with the realization problem of biquadratic impedances, motivated by the recent development in passive mechanical control. This brief generalizes a realization procedure of a special class of biquadratic impedances to a more general form, and the resulting series-parallel RLC networks whose elements are no more than those in Bott-Duffin's networks are obtained without minimization. The realizability condition is proven by providing a constructive synthesis procedure. The series-parallel network obtained contains elements no more than those of Bott-Duffin's network when the impedance is nonregular. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 60-V, >\hbox {225} ^{\circ}\hbox {C} Half-Bridge Driver for Piezoelectric Acoustic Transducer, on SOI CMOS

    Publication Year: 2012 , Page(s): 771 - 775
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1001 KB) |  | HTML iconHTML  

    This brief presents a high-voltage (HV) transducer driver to fulfill the requirement of the proposed high-data-rate down-hole acoustic telemetry system. The driver is targeted to drive a stack of piezoelectric disks modeled as a capacitive load of 0.3 μF and across a broadband from 600 Hz to 1.2 kHz. To ensure stability, the driver is designed as an open-loop system, comprising a dead-time controller, level shifters, gate drivers, and power MOSFETs. The driver is fabricated using the 1.0- μm silicon-on-insulator CMOS process and its performance is investigated up to 260 °C, far beyond the specified process limit of 225 °C. The experimental results also validated the functionality of the HV Class-D-type driver for voltages up to 60 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10-MHz GaN HEMT DC/DC Boost Converter for Power Amplifier Applications

    Publication Year: 2012 , Page(s): 776 - 779
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (859 KB) |  | HTML iconHTML  

    AlGaN/GaN HEMTs show low on-state resistance and small gate capacitances, which makes them good candidates for switching applications. Up to now, their exploitations in dc/dc converters have been largely investigated in high power electronics but with switching frequencies under 1 MHz. In this brief, the potentialities of GaN HEMTs are investigated for high-speed dc/dc converters. To this aim, a 10-MHz GaN 16-34-V boost converter with above-90% efficiency is presented. Such converters are well suited for high-efficiency power amplifiers based on dynamic bias control for high peak-to-average-power-ratio applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Dual Charge Pump for Quiescent Touch Sensor Power Supply

    Publication Year: 2012 , Page(s): 780 - 784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB) |  | HTML iconHTML  

    This brief presents a dual charge pump suitable for touch sensor power supply applications, where a calm standby voltage as well as quick recovery from disturbance is required. The proposed circuit adaptively controls the two parallel-connected charge pumps: a current driving Dickson's charge pump with a pumping capacitor of 95.4 pF and a low-ripple cross-couple charge pump with a capacitor of 10.6 pF. The heavy-duty Dickson's pump turns on for swift recovery from the drastic charge loss and turns off for reduced noise during the hold-and-sensing period. An instantaneous pumping stroke of the charge pump controller and a low dropout following the charge pumps further reduce supply noise. The proposed circuit is fabricated using a 0.18-μm CMOS process. Measurement results show a recharge time shorter than 1 μs and supply noise less than the detection limit. The area penalty is less than 1% compared to a single charge pump. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems

    Publication Year: 2012 , Page(s): 785 - 789
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    Precisely measuring specifications of differential analog and mixed-signal circuits is a difficult problem for self-test development because the imbalance introduced by the design-for-test circuitry on the differential signaling causes nonlinearity on the test stimulus, resulting in degrading device-under-test (DUT) performance. This problem triggers low test accuracy and serious yield loss. This brief proposes a novel test methodology to accurately predict individual DUT specifications by overcoming the imbalance problem with the imbalance generator, a radio-frequency transformer, and a programmable capacitor array based on a loopback test configuration. The imbalance generator produces spectral loopback responses of different weight. Nonlinear equations are then derived to characterize DUT specifications. Hardware measurement results show that this approach can be used to predict the specifications of a DUT in a production test. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances

    Publication Year: 2012 , Page(s): 790 - 794
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1311 KB) |  | HTML iconHTML  

    Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power consumption. We fabricated a 1-Mbit DP-SRAM with WA8T testchip using a 40-nm CMOS process. The proposed WA8T device achieved a 120-mV improvement in VDDmin with less than 1% area overhead. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials

    Publication Year: 2012 , Page(s): 795 - 799
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (654 KB) |  | HTML iconHTML  

    Bit-parallel polynomial basis multipliers over the finite field GF(2m) generated using type-II irreducible pentanomials are considered in this brief. The bit-parallel multipliers presented here have the lowest delay known to date for similar multipliers based on this type of irreducible pentanomials, with a very small increase of XOR gates. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Discrete Model for Correlation Between Quantization Noises

    Publication Year: 2012 , Page(s): 800 - 804
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    The automation of fixed-point conversion requires fast methods to evaluate the numerical accuracy of the system. As an alternative to a simulation-based approach, most of the analytical methods use perturbation theory to provide the expression of the quantization noise at the output of a system. Most existing analytical methods do not consider a correlation between noise sources. This assumption is no longer valid when a unique datum is quantized several times. This brief proposes to study the correlation between quantization noises with different quantization modes (truncation and rounding) and considering the number of eliminated bits. Then, the expression of the power of the output quantization noise is provided when the correlation between the noise sources is considered. The proposed approach allows improving significantly the estimation of the output quantization noise power compared to the classical approach, with a slight increase of the computation time. In our experiment, the maximal relative estimation error obtained with the proposed approach is less than 2% compared to 84% when a correlation is not taken into account. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Perfect Decomposition Narrow-Band FIR Filter Banks

    Publication Year: 2012 , Page(s): 805 - 809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (673 KB) |  | HTML iconHTML  

    This brief introduces perfect decomposition filter banks based on narrow-band linear-phase finite impulse response (FIR) filters. They consist of inner and lateral FIR filters. The inner filters are optimal equiripple narrow-bandpass FIR filters based on isoextremal polynomials. The inner filters are supplemented by lateral narrow-band low- and high-pass FIR filters. The concept of such isoextremal polynomials of this kind enables flexibility in the resulting frequency response of the filter bank. The filter banks presented here are made under the constraint of the resulting frequency response with a constant value for all frequencies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Further Properties and a Fast Realization of the Iterative Truncated Arithmetic Mean Filter

    Publication Year: 2012 , Page(s): 810 - 814
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    The iterative truncated arithmetic mean (ITM) filter has been recently proposed. It possesses merits of both the mean and median filters. In this brief, the Cramer-Rao lower bound is employed to further analyze the ITM filter. It shows that this filter outperforms the median filter in attenuating not only the short-tailed Gaussian noise but also the long-tailed Laplacian noise. A fast realization of the ITM filter is proposed. Its computational complexity is studied. Experimental results demonstrate that the proposed algorithm is faster than the standard median filter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope