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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 1 • Date Jan. 2013

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Displaying Results 1 - 25 of 28
  • Table of Contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2013 , Page(s): C2
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  • Progress update and a look ahead

    Publication Year: 2013 , Page(s): 1 - 2
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  • Modeling of Jitter in Bang-Bang CDR With Fourier Series Analysis

    Publication Year: 2013 , Page(s): 3 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1623 KB) |  | HTML iconHTML  

    Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by the Fourier series analysis and formulating the time domain waveforms. As a result, a new equation is presented to obtain corner frequency. Also, the jitter tolerance is expressed in a closed form as a function of loop parameters. The presented method is general enough to be used for designing the BBCDR. System level simulation is used to validate the analytical results with particular emphasis on jitter transfer and tolerance characteristics. The experiments all show excellent conformance between analytical equations and simulation results. View full abstract»

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  • An Order-Statistics Based Matching Strategy for Circuit Components in Data Converters

    Publication Year: 2013 , Page(s): 11 - 24
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2109 KB) |  | HTML iconHTML  

    Random mismatch errors in matching-critical circuit components cause variability in component parameters, which in turn degrade linearity performance and parametric yield of data converters realized by these components. Utilizing results from the area of order statistics, this paper introduces a novel random mismatch compensation theory called ordered element matching. By pairing a small parameter component with a large one, it effectively reduces the standard deviation of the mismatch errors by a factor of at least 6.5 in a reasonably sized component population. An order-statistics based outlier elimination strategy further improves the standard deviation and more importantly reduces the differential nonlinearity by a factor of 2 or more. Building on these, a new technique called complete-folding is developed, which selectively converts a unary-weighted array to a binary-weighted array and consequently reduces the differential nonlinearity and integral nonlinearity by another factor of more than 3 and 8, respectively. Monte Carlo simulations are performed in a high-resolution data converter design to quantitatively compare the matching performance achieved by complete-folding technique with state of the art. Significant improvements on linearity performance and design cost are obtained. View full abstract»

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  • A Low-Power CT Incremental 3rd Order /spl Sigma//spl Delta/ ADC for Biosensor Applications

    Publication Year: 2013 , Page(s): 25 - 36
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2214 KB) |  | HTML iconHTML  

    This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. View full abstract»

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  • A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

    Publication Year: 2013 , Page(s): 37 - 50
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3076 KB) |  | HTML iconHTML  

    A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-μm CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm. The reference spur of the proposed PLL is measured to be -80 dBc/-74 dBc and an in-band phase noise of -103 dBc/Hz at 100 kHz offset is achieved. View full abstract»

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  • Analytical Approach to the Study of Injection-Locked Frequency Dividers

    Publication Year: 2013 , Page(s): 51 - 62
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2442 KB) |  | HTML iconHTML  

    An analytical method for the nonlinear analysis of injection-locked frequency dividers (ILFDs) is presented based on the method of the slowly-varying amplitude and phase. We introduce a general model of ILFDs and derive the associated averaging equations describing their first-order dynamical behavior. These equations are solved in closed form for two typical injection techniques of ILFDs, namely the injection via tail device and the direct injection. The oscillation amplitude and phase in the locked states and during the transient, as well as the locking range are obtained in explicit form. Numerical simulations validate the presented formulas, which provide useful design insights. View full abstract»

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  • Intrinsic Distortion of a Fully Differential BD-Modulated Class-D Amplifier With Analog Feedback

    Publication Year: 2013 , Page(s): 63 - 73
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    This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs. View full abstract»

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  • A Reconfigurable and Power-Scalable 10–12 Bit 0.4–44 MS/s Pipelined ADC With 0.35–0.5 pJ/Step in 1.2 V 90 nm Digital CMOS

    Publication Year: 2013 , Page(s): 74 - 83
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2056 KB) |  | HTML iconHTML  

    A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V 90-nm digital CMOS technology, this ADC achieves low power (figure-of-merit of FOM=0.35 to 0.5 pJ per A/D conversion step) over its full bandwidth-resolution range. Accordingly, compared to state-of-the-art power-efficient reconfigurable pipelined ADCs, this ADC provides a larger bandwidth-resolution reconfigurability space, while maintaining a highly competitive FOM over this entire space. To achieve such low-power performance in a low-voltage nanometer CMOS process, this work utilizes: (1) a current-scalable frequency-compensation technique to design low-power current-scalable two-stage opamps; (2) a switched-capacitor technique to design dynamic comparators with low input capacitance (input-loading effect); and (3) a low-power digital background gain-calibration technique. The large bandwidth and resolution reconfigurability ranges are achieved using current-scaling and stage-bypass techniques, respectively. View full abstract»

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  • A Novel CMOS Frequency-Mixing Transimpedance Amplifier for Frequency Domain Near Infrared Spectroscopy

    Publication Year: 2013 , Page(s): 84 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2167 KB) |  | HTML iconHTML  

    This paper presents the design and measurement results of a novel frequency-mixing transimpedance amplifier (FM-TIA), which is the key building block towards a monolithically integrated optical sensor front-end for frequency domain near-infrared (NIR) spectroscopy (FD-NIRS). The FM-TIA employs a T-feedback network incorporating a gate-controlled transistor for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The proposed FM-TIA is capable of operating either in the traditional wideband mode or the frequency-mixing mode, depending on the applied gate control voltage. A wideband post amplifier is implemented on chip to characterize both modes for comparative study. The wideband mode achieves 107 dBΩ transimpedance gain with 200 MHz bandwidth for 4 pF photodiode capacitance. The measured total integrated input referred current noise is 158 nArms . When the TIA is modulated by a 100 MHz signal with 0.5 V amplitude in the mixing mode, it achieves 92 dBΩ conversion gain. The measured 1 dB compression point is 3.1 μA and IIP3 is 10.6 μA. The input-referred current noise integrated up to 50 kHz is only 10.4 nArms, which is 15 times lower than the wideband mode noise. The FM-TIA together with the post amplifier draws 23 mA from a 1.8 V power supply, where the output buffer consumes 16.15 mA. View full abstract»

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  • Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps

    Publication Year: 2013 , Page(s): 95 - 107
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2751 KB) |  | HTML iconHTML  

    This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 μA 7-20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240-500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 μm CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 μA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/√ Hz IRN density, and occupies 0.21 mm 2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/√ Hz IRN density, and occupies 0.23 mm 2 silicon area without pads. View full abstract»

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  • A 6.0–13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS

    Publication Year: 2013 , Page(s): 108 - 115
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1370 KB) |  | HTML iconHTML  

    A 6.0-13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply. View full abstract»

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  • A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit

    Publication Year: 2013 , Page(s): 116 - 124
    Cited by:  Papers (1)
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    This paper proposes a high speed bidirectional mixed-voltage I/O buffer using 90 nm 1.2 V standard CMOS process. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit/receive 2 × VDD voltage level signal without any gate-oxide overstress hazard. Most important of all, the gate-oxide overstress hazard is eliminated by adopting a dual-path gate-tracking circuit. The maximum data rate and jitter are measured to be 800 Mbps/12.37 ps and 704 Mbps/14.79 ps for 1.2 V and 2.5 V signal voltage, respectively, with a given capacitive load of 20 pF. View full abstract»

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  • WLS Design of Sparse FIR Digital Filters

    Publication Year: 2013 , Page(s): 125 - 135
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2142 KB) |  | HTML iconHTML  

    In this paper, we propose a novel algorithm for sparse finite impulse response (FIR) filter designs. The objective of the sparse digital filter design problem considered in this paper is to reduce the number of nonzero-valued filter coefficients, subject to a weighted least-squares (WLS) approximation error constraint imposed on the frequency domain. The proposed design method is inspired by the iterative shrinkage/thresholding (IST) algorithms, which are used in sparse and redundant representation for signals. The basic idea of the proposed design algorithm is to successively transform the original nonconvex problem to a series of constrained subproblems in a simpler form. Despite of their nonconvexity, these subproblems can be efficiently and reliably solved in each iterative step by a numerical approach developed in this paper. Furthermore, it can be demonstrated that the obtained solutions are essentially optimal to their respective subproblems. Since its major part only involves scalar operations, the proposed algorithm is computationally efficient. Three sets of numerical examples are presented in this paper to illustrate the effectiveness of the proposed design algorithm. View full abstract»

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  • Two-Rate Based Low-Complexity Variable Fractional-Delay FIR Filter Structures

    Publication Year: 2013 , Page(s): 136 - 149
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2661 KB) |  | HTML iconHTML  

    This paper considers two-rate based structures for variable fractional-delay (VFD) finite-length impulse response (FIR) filters. They are single-rate structures but derived through a two-rate approach. The basic structure considered hitherto utilizes a regular half-band (HB) linear-phase filter and the Farrow structure with linear-phase subfilters. Especially for wide-band specifications, this structure is computationally efficient because most of the overall arithmetic complexity is due to the HB filter which is common to all Farrow-structure subfilters. This paper extends and generalizes existing results. Firstly, frequency-response masking (FRM) HB filters are utilized which offer further complexity reductions. Secondly, both linear-phase and low-delay subfilters are treated and combined which offers trade-offs between the complexity, delay, and magnitude response overshoot which is typical for low-delay filters. Thirdly, the HB filter is replaced by a general filter which enables additional frequency-response constraints in the upper frequency band which normally is treated as a don't-care band. Wide-band design examples (90, 95, and 98% of the Nyquist band) reveal arithmetic complexity savings between some 20 and 85% compared with other structures, including infinite-length impulse response structures. Hence, the VFD filter structures proposed in this paper exhibit the lowest arithmetic complexity among all hitherto published VFD filter structures. View full abstract»

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  • Kron Reduction of Graphs With Applications to Electrical Networks

    Publication Year: 2013 , Page(s): 150 - 163
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3757 KB) |  | HTML iconHTML  

    Consider a weighted undirected graph and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements corresponding to self-loops. The Kron reduction of this graph is again a graph whose Laplacian matrix is obtained by the Schur complement of the original Laplacian matrix with respect to a specified subset of nodes. The Kron reduction process is ubiquitous in classic circuit theory and in related disciplines such as electrical impedance tomography, smart grid monitoring, transient stability assessment, and analysis of power electronics. Kron reduction is also relevant in other physical domains, in computational applications, and in the reduction of Markov chains. Related concepts have also been studied as purely theoretic problems in the literature on linear algebra. In this paper we analyze the Kron reduction process from the viewpoint of algebraic graph theory. Specifically, we provide a comprehensive and detailed graph-theoretic analysis of Kron reduction encompassing topological, algebraic, spectral, resistive, and sensitivity analyses. Throughout our theoretic elaborations we especially emphasize the practical applicability of our results to various problem setups arising in engineering, computation, and linear algebra. Our analysis of Kron reduction leads to novel insights both on the mathematical and the physical side. View full abstract»

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  • Dissipativity Enforcement via Perturbation of Para-Hermitian Pencils

    Publication Year: 2013 , Page(s): 164 - 177
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3093 KB) |  | HTML iconHTML  

    Dissipativity is an important property of individual systems that guarantees a stable interconnected system. However, due to errors in the modeling process weakly non-dissipative models may be constructed. This paper introduces an enhanced method to perturb a non-dissipative LTI system in order to enforce dissipativity using spectral perturbation results for para-Hermitian pencils. Compared to earlier algorithms the new method is applicable to a wider class of problems, it utilizes a simpler framework, and employs a larger class of allowable perturbations resulting in smaller perturbations. Moreover, system stability can be enforced as well. Numerical examples are provided to show the effectiveness of the new approach. View full abstract»

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  • Asymptotic Stability of Two-Dimensional Discrete Systems With Saturation Nonlinearities

    Publication Year: 2013 , Page(s): 178 - 188
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    This paper investigates the asymptotic stability of discrete dynamical systems in a class of two-dimensional (2-D) systems whose dynamical parts are described in the Fornasini-Marchesini model along with a standard saturation operator on the state space. Under the assumption that the stability of the nominal system is ensured by the solvability of a linear matrix inequality, two techniques are introduced for checking the tolerance of the system against saturation effects. One is a quadratic method that accounts for the stability margin of a system. Another is a non-quadratic method that uses the asymptotic property of a majorant nonnegative system. These techniques are useful to improve upon previously known results. Two theorems are introduced in this paper in different manners. The first theorem provides a plain interpretation on the stability condition; however, it requires a two-step process to search for a solution. The second theorem is expressed as a linear matrix inequality, which is the dual statement of the first theorem. These results can be naturally modified for 1-D systems, 2-D systems in the Roesser's model, and multidimensional systems. Illustrative examples show that the two techniques adopted in this paper have different effectiveness in enlarging the scope of application. View full abstract»

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  • Optimal Tracking Performance Limitation of Networked Control Systems With Limited Bandwidth and Additive Colored White Gaussian Noise

    Publication Year: 2013 , Page(s): 189 - 198
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3302 KB) |  | HTML iconHTML  

    This paper studies optimal tracking performance issues for multi-input-multi-output linear time-invariant systems under networked control with limited bandwidth and additive colored white Gaussian noise channel. The tracking performance is measured by control input energy and the energy of the error signal between the output of the system and the reference signal with respect to a Brownian motion random process. This paper focuses on two kinds of network parameters, the basic network parameter-bandwidth and the additive colored white Gaussian noise, and studies the tracking performance limitation problem. The best attainable tracking performance is obtained, and the impact of limited bandwidth and additive colored white Gaussian noise of the communication channel on the attainable tracking performance is revealed. It is shown that the optimal tracking performance depends on nonminimum phase zeros, gain at all frequencies and their directions unitary vector of the given plant, as well as the limited bandwidth and additive colored white Gaussian noise of the communication channel. The simulation results are finally given to illustrate the theoretical results. View full abstract»

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  • Flocking of Multi-Agent Non-Holonomic Systems With Proximity Graphs

    Publication Year: 2013 , Page(s): 199 - 210
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3346 KB) |  | HTML iconHTML  

    Multi-agent systems are ubiquitous in the real-world and have received an increasing attention by many researchers worldwide. A multi-agent system is composed of many agents interconnected by a communication network. This paper aims to further investigate the flocking and preserving connectedness in multi-agent nonholonomic systems with proximity graphs, in which the positions and the relative distances are not available to the distributed controllers. Several sufficient conditions are derived to resolve the above problem based on the kinematic model and the dynamic model, respectively. These sufficient conditions indicate that, for any given distinct initial positions and connected initial graph, there always exist gains of the linear protocols to preserve the connectedness of the graph and realize flocking. Moreover, under an additional condition on initial heading angles, the similar result is obtained for a nonlinear protocol with the form of Kuramoto model. Finally, numerical simulations are given to validate the above theoretical results. View full abstract»

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  • TEAM: ThrEshold Adaptive Memristor Model

    Publication Year: 2013 , Page(s): 211 - 221
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2472 KB) |  | HTML iconHTML  

    Memristive devices are novel devices, which can be used in applications ranging from memory and logic to neuromorphic systems. A memristive device offers several advantages: nonvolatility, good scalability, effectively no leakage current, and compatibility with CMOS technology, both electrically and in terms of manufacturing. Several models for memristive devices have been developed and are discussed in this paper. Digital applications such as memory and logic require a model that is highly nonlinear, simple for calculations, and sufficiently accurate. In this paper, a new memristive device model is presented-TEAM, ThrEshold Adaptive Memristor model. This model is flexible and can be fit to any practical memristive device. Previously published models are compared in this paper to the proposed TEAM model. It is shown that the proposed model is reasonably accurate and computationally efficient, and is more appropriate for circuit simulation than previously published models. View full abstract»

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  • DS-CDMA Implementation With Iterative Multiple Access Interference Cancellation

    Publication Year: 2013 , Page(s): 222 - 231
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1537 KB) |  | HTML iconHTML  

    In this paper an implementation of iterative joint detection for multiple access interference using direct-sequence code-division multiple-access (DS-CDMA) is presented. Results for multiple field programmable gate array (FPGA) platforms and multiple technology nodes for synthesized application specific integrated circuits (ASIC) are presented. The joint detection is performed using a generalized version of interleave-division multiple-access (IDMA) known as partition spreading (PS) CDMA. Decoding is performed using iterative methods from turbo and sum-product decoding. The synthesized ASIC system demonstrates a maximum aggregate throughput of 197 Mb/s for a fully loaded 50-user system, while the implemented FPGA 50-user system has a maximum aggregate throughput of 119 Mb/s. View full abstract»

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  • All-Adaptive Blind Matched Filtering for the Equalization and Identification of Multipath Channels—A Practical Approach

    Publication Year: 2013 , Page(s): 232 - 242
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2508 KB) |  | HTML iconHTML  

    Blind matched filter receiver is advantageous over the state-of-the-art blind schemes due the simplicity in its implementation. To estimate the multipath communication channels, it uses neither any matrix decomposition methods nor statistics of the received data higher than the second order ones. On the other hand, the realization of the conventional blind matched filter receiver requires the noise variance to be estimated and the equalizer parameters to be calculated in state-space with relatively costly matrix operations. In this paper, a novel architecture is proposed to simplify a potential hardware implementation of the blind matched filter receiver. Our novel approach transforms the blind matched filter receiver into an all-adaptive format which replaces all the matrix operations. Furthermore, the novel design does not need for any extra step to estimate the noise variance. In this paper we also report on a comparative channel equalization and channel identification scenario, looking into the performances of the conventional and our novel all-adaptive blind matched filter receiver through simulations. View full abstract»

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  • Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems

    Publication Year: 2013 , Page(s): 243 - 254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2152 KB) |  | HTML iconHTML  

    Conventional digital signal processor (DSP) based digital controllers are not specifically optimized for multi-rail DC-DC converter applications. A new application-specific instruction-set processor (ASIP) that overcomes the shortcomings of existing controllers has thus been designed, implemented, and evaluated. The proposed dual multiply-accumulate (MAC) architecture has been implemented using a field programmable gate array and verified in a closed-loop power converter system. The benefits of the proposed ASIP are illustrated through a comparison with a conventional single MAC processor architecture. Experimental results demonstrate improved output voltage transient response compared with existing DSP-based controllers when controlling multiple DC-DC converters. In the case of multiple converters that have a non-integer switching frequency ratio more significant improvements in transient response are obtained due to the processor's interrupt controller. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras