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Computers and Digital Techniques, IEE Proceedings E

Issue 6 • Date Nov 1993

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Displaying Results 1 - 10 of 10
  • Two-level logic circuits using EXOR sums of products

    Publication Year: 1993 , Page(s): 348 - 356
    Cited by:  Papers (1)
    Click to expandAbstract | PDF file iconPDF (656 KB)  

    Two-level logic is most often implemented as an inclusive-OR sum of product terms, e.g. with PLAs. Using exclusive-OR (EXOR) sums may simplify the representation and manipulation of Boolean functions and result in more easily testable implementations requiring fewer product terms. However, due to the lack of relevant algorithms and efficient implementation structures, it has not been possible to t... View full abstract»

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  • Fault effects in asynchronous sequential logic circuits

    Publication Year: 1993 , Page(s): 327 - 332
    Click to expandAbstract | PDF file iconPDF (480 KB)  

    The paper demonstrates the effects of single stuck-at faults in Huffman-model asynchronous sequential logic circuits (ASLCs). The fault effects include equivalent-state redundant faults, invalid-state redundant faults and state oscillations. Equivalent-state redundant faults in ASLCs may be generated by violation of the fundamental mode constraint noncritical races or delays. On the other hand, in... View full abstract»

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  • Synthesis for Reed-Muller directed acyclic graph network

    Publication Year: 1993 , Page(s): 357 - 360
    Click to expandAbstract | PDF file iconPDF (200 KB)  

    A synthesis algorithm for Reed-Muller directed acyclic graph (DAG) networks is presented. Based on the circuit cost matrix, the algorithm grows the DAG network from inputs to output, and thus allows the formulation of more accurate criteria for variable selection. By using this algorithm, the quasiminimum DAG network can be found with (n+2)(n-1)/2 variable assignments. View full abstract»

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  • Testing check bits at no cost in RAMs with on-chip ECC

    Publication Year: 1993 , Page(s): 304 - 312
    Cited by:  Papers (3)
    Click to expandAbstract | PDF file iconPDF (628 KB)  

    The authors address the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding a class of parity-check matrices that have the property that all the check bits can be tested for pattern-sensitive faults while the information bits are being tested, without... View full abstract»

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  • Strongly fault-secure designs for arithmetic arrays

    Publication Year: 1993 , Page(s): 341 - 347
    Click to expandAbstract | PDF file iconPDF (428 KB)  

    We make a comparative study of two techniques to design error-detectable array architectures. These techniques are the redundant binary representation (RBR) where the data is encoded in the 1-out-of-3 code; and the two-rail logic where the data is encoded in the 1-out-of-2 code. In recent work, the RBR has been used to achieve online error detection and localisation by checking the data on the arr... View full abstract»

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  • Multilevel logic synthesis for PAL devices

    Publication Year: 1993 , Page(s): 313 - 319
    Click to expandAbstract | PDF file iconPDF (476 KB)  

    A system has been developed to perform multilevel logic synthesis onto PALs for designs that will not fit in two-level sum of products form. The procedure is based upon the application of technology dependent selective collapse algorithms on a multilevel circuit. The multilevel circuit may be obtained using a number of different synthesis strategies. The packages have been implemented in C and add... View full abstract»

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  • Minimising the energy of active contour model using a Hopfield network

    Publication Year: 1993 , Page(s): 297 - 303
    Cited by:  Papers (1)
    Click to expandAbstract | PDF file iconPDF (468 KB)  

    Active contour models (snakes) are commonly used for locating the boundary of an object in computer vision applications. The minimisation procedure is the key problem to solve in the technique of active contour models. A minimisation method for an active contour model using Hopfield networks is proposed. Due to its network structure, it lends itself admirably to parallel implementation and is pote... View full abstract»

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  • Cellular logic bus arbitration

    Publication Year: 1993 , Page(s): 289 - 296
    Cited by:  Papers (1)
    Click to expandAbstract | PDF file iconPDF (420 KB)  

    The functional and VLSI design of a novel one-of-N bus arbitration circuit for a time-shared bus-interconnected multiprocessor system is presented. The proposed system is a multilevel, hierarchical, two-bit cellular processor structure. The arbitration protocol of rotating priority has been customised to produce a hierarchical, fairness-oriented, rotating-priority protocol that guarantees efficien... View full abstract»

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  • Trade-offs in developing fault tolerant software

    Publication Year: 1993 , Page(s): 320 - 326
    Cited by:  Papers (1)
    Click to expandAbstract | PDF file iconPDF (504 KB)  

    Design diversity has emerged as a powerful mechanism for incorporating software fault tolerance in ultra-reliable systems. We study the trade-offs available during the development process of fault-tolerant software employing the recovery block approach. When the total available testing time is bounded, our analysis determines how appropriately to allocate testing time to the various redundant modu... View full abstract»

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  • Three-layer router for channels with constrained terminals

    Publication Year: 1993 , Page(s): 333 - 340
    Cited by:  Papers (1)
    Click to expandAbstract | PDF file iconPDF (580 KB)  

    With recent advances in vertical-integration technology, it is now reasonable to consider a three-dimensional IC structure containing either partially or completely stacked active layers. Thus it is possible to have stacked terminals at the channel edges. In this case, each terminal is constrained to a specific layer and therefore may only enter the channel on the layer to which it is constrained.... View full abstract»

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