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Emerging and Selected Topics in Circuits and Systems, IEEE Journal on

Issue 4 • Date Dec. 2012

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Displaying Results 1 - 14 of 14
  • Table of contents

    Page(s): C1
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  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems publication information

    Page(s): C2
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  • Editorial

    Page(s): 653 - 657
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  • A Self-Contained System With CNTs-Based Biosensors for Cell Culture Monitoring

    Page(s): 658 - 671
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    Biosensors have been applied to disparate fields, especially for endogenous compounds such as glucose and lactate. The main areas of application are certainly related to medical and diagnostic purposes. However, metabolic monitoring can be also of interest in cell analysis. Cells can be cultivated for several purposes, such as understanding and modeling some biological mechanisms, the development of new drugs and therapies, or in the ήeld of regenerative medicine. All the aforementioned applications require a thorough knowledge of the biological system under study. In this paper, we propose the development of a self-contained system based on electrochemical biosensors for cell culture monitoring. The detection is based on oxidases immobilized onto carbon nanotubes. We also develop an architecture to record the signal generated by the biosensor and transmit it to a remote station by means of a Bluetooth module. We calibrate the system for glucose and lactate detection in phosphate buffer solution. We achieve a sensitivity of 55.5 μA/mM cm-2 and a detection limit of 2 μM for glucose, as well as a sensitivity of 25.0 μA/ mM cm-2 and a detection limit of 11 μM for lactate. We finally validate the two biosensors for metabolic monitoring in culture medium and we detect lactate production in neuroblastoma cells after 72 h of cultivation. The integrated system proposed in the present work opens new opportunities towards the development of novel tools for cell analysis. View full abstract»

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  • Heterogeneous Integration of Bio-Sensing System-on-Chip and Printed Electronics

    Page(s): 672 - 682
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1850 KB) |  | HTML iconHTML  

    In this paper, we present a heterogeneous integration platform for bio-sensing applications, which seamlessly integrates low-power silicon-based circuits with cost-effective printed electronics. A prototype of wearable Bio-Sensing Node is fabricated to investigate the suitability of this integration approach. A 1.5 ×3.0 mm2 customized mixed-signal system-on-chip (SoC) with the size of is utilized to amplify, digitize, buffer, and transmit the sensed bio-signals. Inkjet printing technology is employed to print nano-particle silver ink on a flexible substrate to fabricate chip-on-ίex, electrodes as well as interconnections. This additive and digital fabrication technology enables fast prototype of the customized electrode pattern. Its high accuracy and fine resolution features allow the direct integration of the bare die (the pad size of 65 μm and pitch size of 90 μm) on the flexible substrate, which significantly miniaturizes the wearable system. The optimal size and layout of printed electrodes are investigated through the in vivo test for electrocardiogram recording applications. The total size of the implemented Bio-Sensing Node is 4.5 ×2.5 μm, which is comparable with a commercial electrode. This inkjet printed heterogeneous integration approach offers a promising solution for the next-generation cost-effective personalized wearable healthcare monitoring devices. View full abstract»

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  • An Optically Powered CMOS Receiver System for Intravascular Magnetic Resonance Applications

    Page(s): 683 - 691
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1931 KB) |  | HTML iconHTML  

    This paper presents a low-power optically powered receiver system designed in 0.18 μm triple well UMC complementary metal-oxide-semiconductor (CMOS) technology. Optical transmission is used for both power delivery and signal transmission. The power of the whole system can be supplied in two different configurations, namely continuous and intermittent mode configurations. In the continuous mode configuration, the optical power of a 650-nm laser source is received and delivered to the electronic circuits by a set of on-chip CMOS photodiodes. In the intermittent mode configuration, a low voltage DC-DC converter is used to boost a single on-chip CMOS photodiode voltage of 0.65 V up to 1.8 V. Additionally, in this configuration, optical switching is used for charging and discharging of a storage capacitor to obtain currents in milliampere range for the proper operation. The front-end part of the receiver consists of a fully differential low noise amplifier (LNA), a fully differential gain stage, a single output double balanced Gilbert-cell mixer, and a laser driver. The front-end part can operate properly by one on-chip photodiode voltage of 0.65 V . System performance is demonstrated for a sample 1.5 T magnetic resonance imaging (MRI) application. Experiments show that LNA of the receiver has a low input referred noise voltage density of 4 nV/√{Hz} at the supply voltage of 0.65 V . The receiver transmits the signal via a fiber-coupled infrared (IR) laser diode (λ = 1310 nm). The results show that the system can continuously process a minimum detectable signal (MDS) of -70 dBm at an incident optical power of 20 mW while the total power consumption of the receiver and the IR diode is 700 μW . In the intermittent mode configuration, the system gain is measured to be 6 dB greater, and the average power consumption is measured as 214 μW when the incident laser is modulated with a rectangular pulse wave of 40 ms period with 95% duty cy- le. View full abstract»

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  • Power Distribution in TSV-Based 3-D Processor-Memory Stacks

    Page(s): 692 - 703
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1853 KB) |  | HTML iconHTML  

    Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a 3-D processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this paper. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to the number of TSVs and decoupling capacitance. View full abstract»

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  • Distributed On-Chip Power Delivery

    Page(s): 704 - 713
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    The performance of an integrated circuit depends strongly upon the power delivery system. With the introduction of ultra-small on-chip voltage regulators, novel design methodologies are needed to simultaneously determine the location of the on-chip power supplies and decoupling capacitors. In this paper, a unified design methodology is proposed to determine the optimal location of the power supplies and decoupling capacitors in high performance integrated circuits. Optimization algorithms widely used for facility location problems are applied in the proposed methodology. The effect of the number and location of the power supplies and decoupling capacitors on the power noise and response time is discussed. View full abstract»

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  • 3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS

    Page(s): 714 - 722
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    3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes (<;650°C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D. View full abstract»

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  • CMOS-3D Smart Imager Architectures for Feature Detection

    Page(s): 723 - 736
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2987 KB) |  | HTML iconHTML  

    This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions. View full abstract»

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  • 2012 Index IEEE Journal on Emerging and Selected Topics in Circuits and Systems Vol. 2

    Page(s): 737 - 747
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  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors

    Page(s): 748
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • [Blank page - back cover]

    Page(s): C4
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Aims & Scope

The IEEE Journal on Emerging and Selected Topics in Circuits and Systems publishes special issues covering the entire Field of Interest of the IEEE Circuits and Systems Society and with particular focus on emerging areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Manuel Delgado-Restituto
Instituto Nacional de Microelectrónica de Sevilla
IMSE-CNM (CSIC/Universidad de Sevilla)