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IEEE Transactions on Electron Devices

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Publication Year: 2012, Page(s):C1 - 3143
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2012, Page(s): C2
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• Miracle Workers—A Round of Much Deserved Applause for the T-ED and EDL Staff

Publication Year: 2012, Page(s):3144 - 3146
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• Kudos to Our Reviewers

Publication Year: 2012, Page(s): 3147
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• Golden List of Reviewers for 2012

Publication Year: 2012, Page(s):3148 - 3177
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• IEEE Journal of Electron Devices Society (J-EDS)

Publication Year: 2012, Page(s): 3178
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• Design, Simulation, and Fabrication of Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) With New Termination Structure

Publication Year: 2012, Page(s):3179 - 3185
Cited by:  Papers (3)
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In this paper, we introduce a new type of termination structure utilizing semi-insulating polycrystalline silicon (SIPOS) structures in conjunction with P- junction extension in order to reduce the area of termination device structure and increase the breakdown voltage. In SIPOS structures, one high-resistance layer is deposited between electrodes on two terminals such that the v... View full abstract»

• A Closed-Form Analytical Transient Response Model for On-Chip Distortionless Interconnect

Publication Year: 2012, Page(s):3186 - 3192
Cited by:  Papers (1)
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This paper presents a closed-form analytical transient response model for an on-chip distortionless interconnect considering resistance/capacitance loads via solving a semi-infinite transmission line equation. As verified by the simulation results, this transient response model has high accuracy, which could be used to derive the characteristics of the transmitted signal for facilitating the desig... View full abstract»

• Thermoelectric Performance of $hbox{Si}_{0.8} hbox{Ge}_{0.2}$ Nanowire Arrays

Publication Year: 2012, Page(s):3193 - 3198
Cited by:  Papers (11)
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The output power of a thin-film thermoelectric generator consisting of a Cu-20- μm nanowire (NW) array (NWA)-Si bulk-Cu sandwich with Si or Si0.8Ge0.2 NWs is measured and compared to Cu-Si bulk-Cu for small temperature differences around room temperature. The array of NWs is made by metal-assisted chemical etching that retains the Ge concentration in the wires. The con... View full abstract»

• Impact of Quantum Confinement on Stress-Induced nMOSFET Threshold Voltage Shift

Publication Year: 2012, Page(s):3199 - 3204
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In this paper, we propose a comprehensive model to express nMOSFET threshold voltage shift induced by stress, ranging from a high tensile one to a high compressive one. Using this model, the quantum confinement effect, combined with large out-of-plane stress, is shown to play an important role to cause the threshold voltage shift as large as about 80 mV induced by high-film-stress contact etch-sto... View full abstract»

• Impact of Quantum Confinement on Gate Threshold Voltage and Subthreshold Swings in Double-Gate Tunnel FETs

Publication Year: 2012, Page(s):3205 - 3211
Cited by:  Papers (18)
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We investigate how the inclusion of quantum confinement in double-gate tunneling field-effect transistors (DG-TFETs) modifies the conventional behavior of electrical parameters of utmost importance in these devices, such as subthreshold swings (point and average) and the gate threshold voltage. We make use of a simple approach that allows us to incorporate a quantum-mechanical description in which... View full abstract»

• High-Throughput Screening of Amorphous $hbox{Y}_{2} hbox{O}_{3}$–$hbox{TiO}_{2}hbox{/}hbox{SiO}_{2}$ Higher $kappa$ Gate Dielectric Layers

Publication Year: 2012, Page(s):3212 - 3216
Cited by:  Papers (2)
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In this paper, an approach using native SiO2 to make amorphous higher dielectric constant films based on the Y2O3-TiO2/SiO2/Si compositional spread libraries by combinatorial pulsed laser deposition is reported. The key feature of the experiment is that combinatorial methodology is used to quickly screen the potential high-dielectric-constant ... View full abstract»

• An Analytical Charge Model for Double-Gate Tunnel FETs

Publication Year: 2012, Page(s):3217 - 3223
Cited by:  Papers (41)
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An analytical charge model for double gate (DG) tunnel FETs (TFETs) is proposed. By splitting the TFET into a series combination of a gated tunnel diode and a DG MOSFET, we solved the Poisson equation with matching boundary conditions to obtain a surface potential model for the DG TFET. Based on that, the source depletion charge and the mobile channel charge are derived. Comparisons between the pr... View full abstract»

• Single Germanium Quantum-dot Placement Along With Self-Aligned Electrodes for Effective Management of Single Charge Tunneling

Publication Year: 2012, Page(s):3224 - 3230
Cited by:  Papers (3)
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We demonstrated the controlled placement of a Ge quantum dot (QD) along with tunnel-junction engineering in a self-organized approach for the effective management of single charge tunneling. In this approach, a single-Ge-QD ( ~ 11 nm) self-aligning with nickel-polycide electrodes is realized by thermally oxidizing a SiGe nanorod that bridges a 15-nm-wide nanotrench in close proximity to electrodes... View full abstract»

• Influence of Edge Defects, Vacancies, and Potential Fluctuations on Transport Properties of Extremely Scaled Graphene Nanoribbons

Publication Year: 2012, Page(s):3231 - 3238
Cited by:  Papers (10)
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Atomistic quantum transport simulations of a large ensemble of devices are employed to investigate the impact of different sources of disorder on the transport properties of extremely scaled (length of 10 nm and width of 1-4 nm) graphene nanoribbons. We report the dependence of the transport gap, on- and off-state conductances, and on-off ratio on edge-defect density, vacancy density, and potentia... View full abstract»

• Experimental Study of Self-Heating Effects in Trigate Nanowire MOSFETs Considering Device Geometry

Publication Year: 2012, Page(s):3239 - 3242
Cited by:  Papers (8)
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Temperature rise by self-heating effects in nanowire (NW) transistors (NW Trs.) is systematically studied with respect to their dependence on the structural parameters. Temperature rise in NW Tr. is found to be independent of the NW size in sub-100-nm regions when compared at the same total power consumption. This is because the heat generated by the drain current is spread to the area larger than... View full abstract»

• Balancing SET/RESET Pulse for $>hbox{10}^{10}$ Endurance in $hbox{HfO}_{2}hbox{/Hf}$ 1T1R Bipolar RRAM

Publication Year: 2012, Page(s):3243 - 3249
Cited by:  Papers (44)
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By tuning the SET/RESET pulse amplitude conditions, the pulse endurance of our 40-nm HfO2/Hf 1T1R resistive-random-access-memory devices demonstrates varying failure behaviors after 106 cycles. For unbalanced SET/RESET pulse amplitude conditions, both low-resistance state (LRS) and high-resistance state (HRS) failures may occur, while varying the pulsewidths influences the LR... View full abstract»

• Monolayer $hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map

Publication Year: 2012, Page(s):3250 - 3254
Cited by:  Papers (77)
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The performance of a 5-nm gate length monolayer MoS2 transistor is benchmarked against an ultrathin body Si transistor of similar dimensions and the ITRS requirements for 2026 low operating power (LOP) technology. The MoS2 transistor has a subthreshold slope of 70 mV/dec, an on -/off-current ratio of 4.8 × 104, a drive current of 238 μA/μm, a p... View full abstract»

• Numerical Simulations of Automatic Change of Threshold Voltage Shift in SRAM With Double-Floating-Gate Structures

Publication Year: 2012, Page(s):3255 - 3262
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We theoretically investigate the self-adjustment mechanism of the threshold voltage shift of the static random access memory (SRAM) based on the double-floating-gate (DFG) structure by considering the capacitive coupling between the neighboring DFGs. We numerically show that the threshold voltage shift is enhanced by the interference between DFGs through the capacitive coupling. The static noise m... View full abstract»

• An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design

Publication Year: 2012, Page(s):3263 - 3268
Cited by:  Papers (13)
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In this paper, an extensive study on the intermodulation distortion and the linearity of gate-material-engineered cylindrical-gate MOSFET (GME CGT MOSFET) has been done, and the influence of technology variations such as channel length and gate material workfunction variations is explored using an ATLAS 3-D device simulator. The simulation results reveal that the GME CGT MOSFET design displays a s... View full abstract»

• Microstructures and Properties of SnZn Lead-Free Solder Joints Bearing La for Electronic Packaging

Publication Year: 2012, Page(s):3269 - 3272
Cited by:  Papers (12)
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In this paper, the effect of rare earth (RE) La on the properties of Sn9Zn solder was carried out. The results indicate that RE La plays an important role not only in the wettability and the structure of the solder but also in the mechanical property of the solder joint. The results show that adding trace amount of RE La can remarkably improve the wettability and oxidation resistance of SnZn solde... View full abstract»

• N-Channel Dual-Workfunction-Gate MOSFET for Analog Circuit Applications

Publication Year: 2012, Page(s):3273 - 3279
Cited by:  Papers (9)
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Analog behaviors of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with dual-workfunction-gate (DWFG) structure are presented. The gate of the n-channel DWFG MOSFET is composed of p+ and n+ poly-Si along the channel carrier flowing direction. To investigate the impact of the proportional length of p- and n-type-doped poly-Si on analog behaviors, they a... View full abstract»

• Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application

Publication Year: 2012, Page(s):3280 - 3287
Cited by:  Papers (21)
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An overall performance comparison analysis based on 2-D Poisson's equation solution has been presented here both for silicon-on-insulator (SOI) and silicon-on-nothing (SON) MOSFET structures. In this paper, for the first time, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented analytically to reduce rollo... View full abstract»

• Flexible Logic Gates Composed of Si-Nanowire-Based Memristive Switches

Publication Year: 2012, Page(s):3288 - 3291
Cited by:  Papers (8)
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The flexible logic circuit configured using Si-based memristive switches is demonstrated. The memristive switches consisting of Ag/a-Si/heavily doped p-type Si are constructed on plastic using top-down-fabricated Si nanowires. The logic gate analyses provide insight toward logic circuits having multifunctionality and high connectivity through a crossbar-array architecture. With the strong s... View full abstract»

• Surface-Potential-Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETs

Publication Year: 2012, Page(s):3292 - 3298
Cited by:  Papers (33)
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A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson's equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao-Sah integral is carried out to obtain the drain current. It is shown that the m... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

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Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy