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Circuits, Devices & Systems, IET

Issue 5 • Date Sept. 2012

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Displaying Results 1 - 12 of 12
  • Editorial - Secial issue on thermal, power and timing modeling, design and simulation

    Page(s): 271 - 272
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (75 KB)  

    The pessimistic low-power system design, assuming a worst-case power dissipation scenario, has been supplanted by a more comprehensive philosophy also known as poweraware, energy-aware or energy-quality scalable design. The idea behind these approaches is to target a system that scales its energy and/or power needs according to different external conditions and the quality requirements. View full abstract»

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  • Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution

    Page(s): 273 - 278
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach. View full abstract»

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  • Low-power processor architecture exploration for online biomedical signal analysis

    Page(s): 279 - 286
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations exist. To this end, a single-and a multi-core architecture are proposed and compared. The single-core architecture is composed of one ULP processing core, an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of several ULP processing cores, individual IMs for each core, a shared DM and an interconnection crossbar between the cores and the DM. These architectures are compared with respect to power/performance trade-offs for different target workloads of online biomedical signal analysis, while exploiting near threshold computing. The results show that with respect to the single-core architecture, the multi-core solution consumes 62% less power for high computation requirements (167 MOps/s), while consuming 46% more power for extremely low computation needs when the power consumption is dominated by leakage. Additionally, the authors show that the proposed ULP processing core, using a simplified instruction set architecture (ISA), achieves energy savings of 54% compared to a reference microcontroller ISA (PIC24). View full abstract»

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  • Using unified power format standard concepts for power-aware design and verification of systems-onchip at transaction level

    Page(s): 287 - 296
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (953 KB)  

    Building efficient and correct system power-management strategies relies on efficient power architecture decision making as well as respecting structural dependencies induced by such architecture. Transaction level modelling allows a rapid exploration, verification and evaluation of alternative power-management architectures and strategies. This study introduces an efficient methodology for making system power decisions at transaction level (TL) by adding and verifying power intent and management capabilities into TL models. A generic framework that abstracts relevant concepts of the IEEE 1801 unified power format standard and implements assertion-based contracts is used throughout the methodology. A TL-model example is considered to validate the methodology. View full abstract»

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  • Worst-case temperature analysis for different resource models

    Page(s): 297 - 307
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (573 KB)  

    The rapid increase in heat dissipation in real-time systems imposes various thermal issues. For instance, real-time constraints cannot be guaranteed if a certain threshold temperature is exceeded, as it would immediately reduce the system reliability and performance. Dynamic thermal management techniques are promising methods to prevent a system from overheating. However, when designing real-time systems that make use of such thermal management techniques, the designer has to be aware of their effect on both real-time constraints and worst-case peak temperature. In particular, the worst-case peak temperature of a real-time system with non-deterministic workload is the maximum possible temperature under all feasible scenarios of task arrivals. This study proposes an analytic framework to calculate the worst-case peak temperature of a system with general resource availabilities, which means that computing power might not be fully available for certain time intervals. The event and resource models are based on real-time and network calculus, and therefore, our analysis method is able to handle a broad range of uncertainties in terms of task arrivals and available computing power. Finally, we propose an indicator for the quality of the resource model with respect to worst-case peak temperature and schedulability. View full abstract»

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  • Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip

    Page(s): 308 - 321
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1238 KB)  

    Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology offers greater device integration and shorter interlayer interconnects. 3D networks-on-chip (NoC)-bus hybrid mesh architecture, which is a hybrid between packet-switched network and a bus, was proposed to take advantage of the intrinsic attributes of 3D ICs. Even though this architecture was proposed as a feasible one to provide both performance and area benefits, the challenges of combining both media (NoC and bus) to design 3D NoCs have not been addressed. In this study, an efficient 3D NoC architecture is proposed to optimise performance, power consumption and reliability of 3D NoC-bus hybrid mesh system. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called `AdaptiveZ' for vertical communication. In addition, the authors propose thermal-aware scheduling strategy in order to mitigate temperature by herding most of the switching activity closer to the heatsink. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10% and negative exponential distribution traffic patterns. In addition, a videoconference encoder has been used as a real application for system analysis. Compared with a typical stacked mesh 3D NoC, our extensive simulations demonstrate significant power, performance and peak temperature improvements. View full abstract»

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  • Power profiling-guided floorplanner for 3D multi-processor systems-on-chip

    Page(s): 322 - 329
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (314 KB)  

    Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in `traditional` thermal-aware floorplanners. View full abstract»

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  • Iterative timing analysis based on nonlinear and interdependent flipflop modelling

    Page(s): 330 - 337
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    In this paper, the authors build a new modelling framework for the timing behaviour of a flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the data/clock alignment of the flipflop. This new framework opens new perspectives into the functioning of a digital circuit by viewing it as a fully interconnected and interdependent system. Consequently, the traditional method for timing analysis is rendered insufficient. An iterative timing analysis method is then developed to solve two related problems. One is to check whether a circuit can work at a given clock period; the other is to determine the minimal clock period of a circuit. Experimental results show that a reduction of the clock period is achieved and its significance is observed especially when process variation is considered. View full abstract»

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  • Integrator clamping for asynchronous sigma-delta modulator central frequency increment

    Page(s): 338 - 346
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1283 KB)  

    Hysteretic comparator (Schmitt trigger) is the basic part of the asynchronous sigma-delta modulator (ASDM). If propagation delay of a hysteretic comparator is not equal to zero and it has measurable value, than it affects the ASDM output frequency spectrum. As ASDM is a circuit with serial connection of an integrator and a hysteretic comparator followed by a negative feedback loop, propagation delay of the comparator will introduce the timing errors in ASDM output signal-triggering events. Therefore ASDM central frequency will be lower then it is in the case for propagation delay equal to zero. This study provides mathematical analysis of the hysteretic comparator propagation delay influence to the ASDM output frequency spectrum. The method for ASDM central frequency improvement using integrator voltage clamping has been proposed. Mathematical analysis, together with simulation and measurement results, shows partial central frequency increment. As ASDM circuit can be used as an oscillator for zero-input signals, central frequency improvement can be significant. View full abstract»

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  • Secure D flip-flop against side channel attacks

    Page(s): 347 - 354
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    Side-channel attacks (SCAs) are a serious threat against security of cryptographic algorithms. Most of the countermeasures proposed to protect cryptosystems against these attacks, are efficient but present a significant area and power consumption overhead. The registers being the main weakness of cryptosystems, the source of leaks the more easily exploitable, we proposed a secure DFF that reduces leaks. In this study, the authors present this countermeasure that considerably increases the robustness of cryptographic algorithms against SCAs. Moreover, the area and power overhead of our secure DFF in a cryptosystem is attractive. View full abstract»

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  • Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime

    Page(s): 355 - 365
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (916 KB)  

    Power consumption has become a major cause of concern spanning from data centres to handheld devices. Traditionally, improvement in power-performance efficiency of a modern superscalar processor came from technology scaling. However, that is no longer the case. Many of the current systems deploy coarse grain voltage and/or frequency scaling for power management. These techniques are attractive, but limited because of their granularity of control and effectiveness in nano-complementary metal-oxide-semiconductor (CMOS) technologies. This study proposes a novel architecture-level mechanism to exploit intra-thread variations for power-performance efficiency in modern superscalar processors. This class of processors implement several buffer/queue structures to support speculative out-of-order execution for performance enhancement. Applications may not need full capabilities of such structures at all times. A mechanism that collaboratively adapts a finite set of key hardware structures to the changing programme behaviour can allow the processor to operate with heterogeneous power-performance capabilities. This study presents a novel offline regression-based empirical model to estimate structure resizing for a selected set of structures. It is shown that using a few processor runtime events, the system can dynamically estimate structure resizing to exploit power-performance efficiency. Results show that using the proposed empirical model, a selective set of key structures can be resized at runtime to deliver on average 40% power-performance efficiency over a baseline design, with only 5% loss of performance. View full abstract»

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  • On-chip process variation-tracking through an all-digital monitoring architecture

    Page(s): 366 - 373
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (641 KB)  

    In sub-nanometer complementary metal oxide semiconductor (CMOS) technologies, process variability strongly affects the fabrication yield. To face this problem, post-silicon adaptive approaches have been proposed as a promising solution. However, their actual implementation requires the availability of effective monitoring architectures that can sense and sample process variation across the die. In this study, the authors present a sensor circuit for capturing on-chip variations owing to the fabrication process. The proposed solution is based on the concept of `variation amplification` and uses the propagation delay measurement through a pass-transistor chain. Our monitor architecture, which consists of a self-contained cell containing N- and P-type sensors along with an all-digital delay measurement circuitry, is able to capture local variations of negative metal oxide semiconductors and positive metal oxide semiconductors transistors individually, therefore enabling fine tuning of the circuit. The authors also propose an array-based integration of the monitors, where the sensors are placed in a different location of the die and connected together with the scan-chain to distribute the sampled data. Detailed SPICE level simulations conducted on an industrial 45-nm CMOS technology demonstrate the sensing capability of the proposed architecture and the effectiveness of the on-chip all-digital measurement process. View full abstract»

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Aims & Scope

IET Circuits, Devices & Systems covers circuit theory and design, circuit analysis and simulation, computer aided design,  filters, circuit implementations, cells and architectures for integration.

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