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Semiconductor Manufacturing, IEEE Transactions on

Issue 4 • Date Nov. 2012

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Displaying Results 1 - 23 of 23
  • Table of contents

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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): C2
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  • Editorial Special Section on the 2011 International Conference on Microelectronic Test Structures

    Page(s): 541
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  • Design and Operation of an Integrated High-Temperature Measurement Structure

    Page(s): 542 - 548
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6349 KB) |  | HTML iconHTML  

    Accurate prediction of the temperature of DMOS transistors used in automotive and industrial power integrated circuits has become critical as these devices are operated at ever increasing power densities. Correct temperature modeling of these devices up to thermal runaway has to be backed by experimental DMOS characterization at high temperatures. In this paper, we present a test setup used for device characterization up to 500$^{circ}{rm C}$. The temperature control is achieved via on-chip integrated heating elements and can be deployed for both on-wafer and packaged device testing, without the need of a protective atmosphere and external heating elements. View full abstract»

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  • A Novel BJT Structure Implemented Using CMOS Processes for High-Performance Analog Circuit Applications

    Page(s): 549 - 554
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9280 KB) |  | HTML iconHTML  

    In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density $J_{C}$ and current gain $beta$ of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics of the collector current $(A_{rm IC})$ and the current gain $(A_{beta})$ for the proposed structure are improved by about 31% and 24%. The improved matching characteristic of the proposed structure is believed to be due to the reduced effect of the deep n-well or the reduced current path from emitter to collector. View full abstract»

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  • Robust Parameter Extraction for the R3 Nonlinear Resistor Model for Diffused and Poly Resistors

    Page(s): 555 - 563
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3997 KB) |  | HTML iconHTML  

    This paper presents robust algorithms to determine the parameters of the R3 nonlinear resistor model for both diffused and poly resistors. Extraction of many R3 parameters is simplified if it is based on the zero-bias conductance $G_{0}$, because $G_{0}$ is not affected by velocity saturation or self-heating. We present techniques to reliably determine $G_{0}$, even when measured data are noisy or highly nonlinear, and show how to extract basic resistance parameters, temperature coefficients, and depletion pinching parameters using $G_{0}$. We describe how to determine thermal conductance parameters, and present a final parameter optimization strategy that prevents imprecision in modeling $G_{0}$ from compromising the accuracy of fitting resistor nonlinearity. View full abstract»

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  • Mechanical–Electrical Measurements and Relevant Test Structures for Sensing Interconnect Stress Effects in CMOS Technology

    Page(s): 564 - 570
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7875 KB) |  | HTML iconHTML  

    For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active regions of silicon. Coupled mechanical–electrical measurements are performed to evaluate the impact of stress at circuit and device levels. This mismatch originated by interconnects metal lines stress is measured through the use of piezoresistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach. View full abstract»

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  • Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation

    Page(s): 571 - 580
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4264 KB) |  | HTML iconHTML  

    This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation. View full abstract»

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  • Lateral-Transistor Test Structures for Evaluating the Effectiveness of Surface Doping Techniques

    Page(s): 581 - 588
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3975 KB) |  | HTML iconHTML  

    This paper presents a lateral-transistor test structure for evaluating the effectiveness of surface doping techniques used to fabricate ultrashallow diodes and ohmic contacts. The test structure requires very limited processing, and simple $I$ $V$ measurements provide a separation of the hole and electron currents across the junction under investigation. The theoretical behavior is verified by Sentaurus simulations. The ability to discern between Schottky-like and pn-junction diodes is demonstrated by the measurement of a series of junctions fabricated by arsenic dopant deposition plus laser annealing. The activation and drive-in of the deposited arsenic is tuned by the laser energy. The anomalous behavior theoretically predicted for very thin, lightly-doped junctions is observed experimentally. Considerations for an optimal design of the test structures are given. View full abstract»

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  • A Markov Chain Framework for Cycle Time Approximation of Toolsets

    Page(s): 589 - 597
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (661 KB) |  | HTML iconHTML  

    Cycle time is a key performance measure in semiconductor manufacturing. Currently, discrete event simulation and queueing theory are the most common approaches to estimating the cycle time of a fabrication facility. However, the performance of both approaches has been unsatisfactory due to many factors, including the inability to perform in an environment where informal and unwritten operational rules exist. Such rules create dependence between the arrival and service processes of a toolset, and, hence, render the classical queueing models inaccurate. We propose a Markov chain framework that attempts to approximate the cycle time of a toolset in the presence of informal operational rules, and we compare our approach with classical queueing models through a series of numerical examples. View full abstract»

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  • Development of an AVM System Implementation Framework

    Page(s): 598 - 613
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (21567 KB) |  | HTML iconHTML  

    Automatic virtual metrology (AVM) is the highest-level of technology for VM applications from the perspective of automation. It enables the fast application of VM to all pieces of equipment in a factory. The existing VM-related literature mainly focuses on creating VM models for manufacturing processes using different algorithms or methods and illustrating the defect-detection capability or the VM conjecture accuracy. Only a few of them mentioned how to implement the AVM system, but with limited details. This paper aims to present the development of an AVM system implementation framework (AVMSIF) to fill this gap. The proposed AVMSIF, together with the developed server-creation approach and XML-based system-operational mechanisms, can allow the complex AVM system to be created in a systematic and easy manner. Also, by adopting plug-and-play interfaces and desired functional modules, the AVMSIF can be applied to different types of equipment in the factory-wide VM deployment. According to the proposed AVMSIF, an AVM system has been successfully created and deployed in our cooperative thin-film-transistor-liquid-crystal-display (TFT-LCD) factory to confirm the effectiveness of the proposed AVMSIF. The results of this paper may be a useful reference for high-tech industries, such as semiconductor and TFT-LCD industries, in the construction of their AVM systems. View full abstract»

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  • Designing a Variable EWMA Controller for Process Disturbance Subject to Linear Drift and Step Changes

    Page(s): 614 - 622
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5449 KB) |  | HTML iconHTML  

    Linear drift and step changes are two commonly encountered disturbances in many semiconductor manufacturing processes. The former may be typically caused by the aging of equipment or tool wearing, while the latter may be caused by using different batches of raw material, preventive maintenance, and sudden changes in manufacturing environment, which are prevalent in the integrated circuit industries. However, most of the existent literature on run-to-run controls has only dealt with processes with linear drift or step changes. Until now, there has been no efficient run-to-run controller to simultaneously adjust the process with these disturbances. In this paper, we first derive the stability conditions and optimal sequence of variable discount factors of the modified variable exponentially weighted moving average controller analytically. Next, we demonstrate that the proposed method is capable of reducing total mean square error (TMSE) of the process output efficiently when both types of process disturbances are present. Finally, a comprehensive comparison is presented to address the process performance of the proposed method compared to the conventional method. The results demonstrate that the proposed method is quite robust in that it is able to reduce the process TMSE even when the process parameters are not accurately estimated. View full abstract»

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  • Hydrogen Peroxide Removal From Chemical–Mechanical Planarization Wastewater

    Page(s): 623 - 629
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1499 KB) |  | HTML iconHTML  

    The goal of this paper was to identify and investigate a practical method for removing hydrogen peroxide from wastewater generated during chemical and mechanical planarization of integrated circuits. Rates of hydrogen peroxide destruction were investigated using: 1) ultraviolet (UV) light; 2) electrochemical reduction and oxidation; 3) two activated carbon catalysts; and 4) a pyrolusite catalyst. The effects of ethylenediaminetetraaceticacid (EDTA), ethylenediamine (ED), and dissolved copper ions on rates of ${rm H}_{2}{rm O}_{2}$ destruction were also investigated. Hydrogen peroxide destruction rates using UV light and the electrochemical reactor were too slow to be useful in a practical treatment scheme. Both activated carbon and pyrolusite catalysts produced fast rates of ${rm H}_{2}{rm O}_{2}$ destruction. However, the presence of EDTA and ED decreased reaction rates on activated carbon, whereas rates on pyrolusite were unaffected. Column experiments with the pyrolusite yielded greater than 99.9% ${rm H}_{2}{rm O}_{2}$ destruction using empty bed contact times as short as 1 min. View full abstract»

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  • Laser-Induced Plasma Exposure on Extreme Ultraviolet Lithography Masks: Damage Analysis

    Page(s): 630 - 637
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3791 KB) |  | HTML iconHTML  

    Extreme ultraviolet lithography (EUVL) is considered as a possible next-generation lithography technology for sub-22-nm feature fabrication. Fabrication of zero printing defect mask blanks is one of the key challenges identified for EUVL under 16 nm. One proposed cleaning mechanism is based on laser-induced plasma (LIP) shock waves in which selective nanoparticle removal is possible. However, due to both shockwave thermomechanical loading and radiation intensity heating from the LIP core during cleaning, there have been concerns over substrate damage. In this paper, computational and experimental damage studies are conducted for assessing damage risk of LIP exposure to EUVL blank samples. Based on a finite element analysis, it is found that the level of radial stress on the surface of nanofilm and nanofilm layers is the critical parameter identified in both excitation mechanisms leading to mechanical material failure. Experimentally, it is determined that above a critical LIP clearance distance, no substrate damage is observed for the EUVL blank during cleaning regardless of the number of laser shots. It is concluded that pressure amplification methods and creation of residual radial tension in nanofilms could be employed to extend EUVL mask damage threshold for LIP exposure during cleaning. View full abstract»

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  • A Predictive Maintenance System for Epitaxy Processes Based on Filtering and Prediction Techniques

    Page(s): 638 - 649
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6779 KB) |  | HTML iconHTML  

    Silicon epitaxial deposition is a process strongly influenced by wafer temperature behavior, which has to be constantly monitored to avoid the production of defective wafers. However, temperature measurements are not reliable, and the sensors have to be appropriately calibrated with some dedicated procedure. A predictive maintenance (PdM) system is proposed with the aim of predicting process behavior and scheduling control actions on the sensors in advance. Two different prediction techniques have been employed and compared: the Kalman predictor and the particle filter with Gaussian kernel density estimator. The accuracy of the PdM module has been tested on real industrial production datasets. View full abstract»

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  • 3-D Simulator of Laser Crystallization for Polycrystalline-Silicon Thin-Film Transistors

    Page(s): 650 - 656
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    A 3-D simulator of laser crystallization for polycrystalline-silicon thin-film transistors has been developed. Random nucleation, crystal growth velocity, latent heat emission, and partial crystallization are modeled, and a 2-D algorithm is extended to a 3-D algorithm. The $mu$-Czochralski technique is analyzed using the 3-D simulator, and it is found that the grain size becomes large when the initial temperature is high after the laser irradiation. View full abstract»

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  • Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization

    Page(s): 657 - 663
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    The dependence of dynamic random access memory (DRAM) device performance on trench and stack cell structures was first observed by changing the process position of passivation annealing. For the trench DRAM, the data retention fail bit counts (FBCs) decreased by 18% and the cell transistor threshold voltage (CTVth) shift by 53 mV. The FBCs are primarily influenced by the junction leakage current. In contrast, for the stack DRAM, the data retention FBCs increased by 225% and the CTVth shift increased by 20 mV. The FBCs are primarily influenced by the gate-induced drain leakage (GIDL) current because of the large gate and the drain overlap region in the recess channel array transistor (RCAT). The interface states increased after the deposition of the plasma nitride layer, as observed in the charge pumping measurement in the trench DRAM. Transmission electron microscopy indicated that the gate oxide thickness in the bottom region of the RCAT is thinner to generate gate oxide leakage. Furthermore, a decrease in the activation energy from 0.64 to 0.55 eV implies the occurrence of GIDL current, which corresponds to the FBC analysis result. This paper demonstrated that the passivation annealing position requires careful adjustment for device and manufacturing optimization. View full abstract»

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  • Design, Fabrication, and Characterization of Ni/4H-SiC (0001) Schottky Diodes Array Equipped With Field Plate and Floating Guard Ring Edge Termination Structures

    Page(s): 664 - 672
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    In this paper, a through process for a commercial fabrication of a Schottky diodes array on thick epitaxial (50 $mu{rm m}$) 4H-SiC (0001) is presented. Nickel was used as a Schottky contact, while a tri-layer of Ti/Pt/Au was considered for ohmic contact metallization. An oxide field plate edge termination and floating metal guard ring was integrated simultaneously in each device structure. Moreover, to improve the device reliability, an optimum thickness of field plate (composite layer of thermally grown oxide and plasma enhanced chemical vapor deposition oxide) was introduced. The process-induced carbon-oxides contamination was eradicated by vacuum annealing at a mild temperature. The critical values of device parameters, such as leakage current, breakdown voltage $(V_{BV})$, Schottky barrier height $(phi_{B})$, ideality factor $(eta)$, and epitaxial doping concentration $(N_{D})$, were obtained from experimentally measured current–voltage $(I{hbox{--}}V)$ and capacitance–voltage $(C{hbox{--}}V)$ characteristics. The data revealed that $phi_{B}$, $eta$, $V_{BV}$, and reverse leakage current are 1.34 eV, 1.21, ${>}{rm 800}~{rm V}$, and 900 pA (at ${-}{rm 100}~{rm V}- ), respectively, which suits most commercial aspects. View full abstract»

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  • Open Access [advertisement]

    Page(s): 673
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  • IEEE Foundation

    Page(s): 674
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  • 2012 IEEE membership application

    Page(s): 675 - 676
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  • 2012 Index IEEE Transactions on Semiconductor Manufacturing Vol. 25

    Page(s): 677 - 689
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  • IEEE Transactions on Semiconductor Manufacturing information for authors

    Page(s): C3
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721