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IEEE Transactions on Computers

Issue 10 • Date Oct. 1985

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Displaying Results 1 - 15 of 15
  • Preface

    Publication Year: 1985, Page(s): 873
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    Freely Available from IEEE
  • Iterative solution of large, sparse linear systems on a static data flow architecture: Performance studies

    Publication Year: 1985, Page(s):874 - 880
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1505 KB)

    The applicability of static data flow architectures to the iterative solution of sparse linear systems of equations is investigated. An analytic performance model of a static data flow computation is developed. This model includes both spatial parallelism, concurrent execution in multiple PEs, and pipelining, the streaming of data from array memories through the PEs. The performance model is used ... View full abstract»

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  • Distributed execution of functional programs using serial combinators

    Publication Year: 1985, Page(s):881 - 891
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2270 KB)

    A general strategy for automatically decomposing and dynamically distributing a functional program is discussed. The strategy is suitable for parallel execution on multiprocessor architectures with no shared memory. It borrows ideas from data flow and reduction machine research on the one hand, and from conventional compiler technology for sequential machines on the other. One of the more troubles... View full abstract»

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  • Fat-trees: Universal networks for hardware-efficient supercomputing

    Publication Year: 1985, Page(s):892 - 901
    Cited by:  Papers (321)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2279 KB)

    The author presents a new class of universal routing networks, called fat-trees, which might be used to interconnect the processors of a general-purpose parallel supercomputer. A fat-tree routing network is parameterized not only in the number of processors, but also in the amount of simultaneous communication it can support. Since communication can be scaled independently from the number of proce... View full abstract»

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  • Fault location techniques for distributed control interconnection networks

    Publication Year: 1985, Page(s):902 - 910
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2371 KB)

    One class of networks suitable for use in parallel processing systems is the multistage cube network. The authors focus on fault location procedures suitable for use in networks that use distributed routing control through the use of routing tags and message transmission protocols. Faults occurring in the data lines can corrupt message routing tags transmitted over them and thereby cause misroutin... View full abstract»

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  • A comparative study of unification algorithms for OR-parallel execution of logic languages

    Publication Year: 1985, Page(s):911 - 917
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1555 KB)

    As a step toward designing a computer architecture suitable for executing parallel logic languages, the author has studied some memory management techniques proposed for creating multiple binding environments, which are required with OR-parallelism. Three algorithms have been implemented using a Prolog-like interpreter and have been tried on some logic programs, to attempt to compare their relativ... View full abstract»

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  • Bandwidth availability of multiple-bus multiprocessors

    Publication Year: 1985, Page(s):918 - 926
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1776 KB)

    The effect of failures on the performance of multiple-bus multiprocessors is considered. Bandwidth expressions for this architecture are derived for uniform and nonuniform memory references. Mathematical models are developed to compute the reliability and the performance-related bandwidth availability (BA). The results obtained for the multiple-bus interconnection are compared with those of a cros... View full abstract»

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  • An empirical study of automatic restructuring of nonnumerical programs for parallel processors

    Publication Year: 1985, Page(s):927 - 933
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1734 KB)

    The feasibility of automatic restructuring of nonnumerical programs for parallel processing is studied through experiments using Parafrase, an automatic restructurer at the University of Illinois, Urbana-Champaign. Parallel processing speedup results due to automatic restructuring for several basic nonnumerical problems are presented. The loops encountered are classified at a low level. On the bas... View full abstract»

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  • A semi-Markov model for the performance of multiple-bus systems

    Publication Year: 1985, Page(s):934 - 942
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1628 KB)

    A discrete-time model is presented of memory interference in multiprocessor systems using multiple-bus interconnection networks. It differs from earlier models in its ability to model variable connection time and arbitrary inter-request time. The model describes each processing element's behavior by means of a semi-Markov process, taking as input the number of processing elements, the number of me... View full abstract»

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  • “Hot spot” contention and combining in multistage interconnection networks

    Publication Year: 1985, Page(s):943 - 948
    Cited by:  Papers (231)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1471 KB)

    The combining of messages within a multistage switching network has been proposed to reduce memory contention in highly parallel shared-memory multiprocessors, especially for shared lock and synchronization data. A quantitative investigation of the performance impact of such contention and the effectiveness of combining in reducing this impact is reported. The effect of a nonuniform traffic patter... View full abstract»

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  • On the effective bandwidth of interleaved memories in vector processor systems

    Publication Year: 1985, Page(s):949 - 957
    Cited by:  Papers (38)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1799 KB)

    Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processor systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth. The authors present some analytical results for the calculation of the resulting effect bandwidth for one and two acce... View full abstract»

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  • On testing isomorphism of permutation networks

    Publication Year: 1985, Page(s):958 - 962
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1243 KB)

    The problem of constructing equivalence maps between two multistage permutation networks is considered. A branch-and-bound algorithm is given to test whether two such networks are equivalent in polynomial time. Whenever they are, the algorithm also determines a map that conjugates one network onto the other. View full abstract»

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  • Performance of parallel branch-and-bound algorithms

    Publication Year: 1985, Page(s):962 - 964
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (867 KB)

    Consideration is given to the performance of parallel best-bound-first branch-and-bound algorithms in which several nodes with least lower bounds are expanded simultaneously. It is well known that anomalies may occur in the execution of a parallel branch-and-bound algorithm. The authors show the conditions under which anomalies are guaranteed not to occur when the number of processors is doubled, ... View full abstract»

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  • The power of parallel prefix

    Publication Year: 1985, Page(s):965 - 968
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (957 KB)

    The prefix computation problem is to compute all n initial products a1* . . . *a1,i=1, . . ., n of a set of n elements, where * is an associative operation. An O(((logn) log(2n/p))XI(n/p)) time deterministic parallel algorithm using pn processors is presented to solve the prefix... View full abstract»

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  • A cache-based multiprocessor with high efficiency

    Publication Year: 1985, Page(s):968 - 972
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1118 KB)

    Shared-memory multiprocessors to support concurrent languages for general-purpose multitasked systems are analyzed. To solve the traditional performance problems caused by memory access latency and conflicts, extensive caching of instructions and data is performed in each processor mode. Caches are private to each processor, and coherence is maintained in hardware between the caches. To maintain a... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org