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Computers, IEEE Transactions on

Issue 2 • Date Feb. 1981

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Displaying Results 1 - 17 of 17
  • A fast parallel algorithm for routing in permutation networks

    Page(s): 93 - 100
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    An algorithm is given for routing in permutation networks-that is, for computing the switch settings that implement a given permutation. The algorithm takes serial time O(n(log N)2) (for one processor with random access to a memory of O(n) words) or parallel time O((log n)3) (for n synchronous processors with conflict-free random access to a common memory of O(n) words). These time bounds may be reduced by a further logarithmic factor when all of the switch sizes are integral powers of two. View full abstract»

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  • Data broadcasting in SIMD computers

    Page(s): 101 - 107
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    Considers the data broadcasting problem for single instruction stream, multiple data stream (SIMD) computers. Two versions of this problem, i.e., random access read (RAR) and random access write (RAW) are considered. Efficient data broadcasting algorithms are developed for both cases. For the case of a RAR, the complexity of the algorithm is O(q2n) on a q-dimensional nq PE mesh-connected computer and 0(log2N) on an N PE cube-connected or perfect shuffle computer. For the case of a RAW, the complexity of the algorithm is 0(q2n+dqn) on a q-dimensional MCC and 0(log2N+d log N) on an N PE cube-connected or perfect shuffle computer; d is the maximum number of data items written into any one PE. View full abstract»

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  • General theory of metastable operation

    Page(s): 107 - 115
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    Metastable operation is a fundamental phenomenon of sequential networks that process asynchronous inputs. Nevertheless, because of its subtle nature and the relatively low probability of its occurrence in conventional systems, this phenomenon is neither well understood nor widely appreciated. With continuing advances in digital technology, however, there is a growing interest in large-scale highly parallel systems. Such systems are likely to involve numerous high-frequency asynchronous interactions, which may result in frequent measures to prevent such failures. In recent years, a number of researchers have been working with some success to develop techniques for dealing with this failure mode. The purpose of this paper is to present a comprehensive theory of metastable operation that may lead to a better understanding of this phenomenon and provide theoretical support for further work in this area. View full abstract»

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  • Kronecker products and shuffle algebra

    Page(s): 116 - 125
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    Relates three classical concepts, viz. mixed radix number system, Kronecker product of matrices, and perfect shuffle. It presents an algebra which describes the hardware organization of the computation of a product Mv, where M is a matrix in Kronecker product form and v is a vector. The algebraic formalism describes both the blockwise structure of the computation and the various possible connection patterns. View full abstract»

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  • P-functions: A new tool for the analysis and synthesis of binary programs

    Page(s): 126 - 134
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    Considers the realization of switching functions by programs composed of certain conditional transfers (binary programs). Methods exist for optimizing binary trees, i.e. binary programs without reconvergent instructions. This paper studies methods for optimizing binary simple programs (programs with possible reconvergent instructions, but where a variable may be tested only once during a computation) and binary programs. The hardware implementations of these programs involve either multiplexers or demultiplexers and OR-gates. View full abstract»

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  • Universality considerations in VLSI circuits

    Page(s): 135 - 140
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    The problem of embedding the interconnection pattern of a circuit into a two-dimensional surface of minimal area is discussed. Since even for some natural patterns graphs containing m connections may require Ω(m2) area, in order to achieve compact embeddings restricted classes of graphs have to be considered. For example, arbitrary trees (of bounded degree) can be embedded in linear area without edges crossing over. Planar graphs can be embedded efficiently only if crossovers are allowed in the embedding. View full abstract»

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  • A generalized algorithm for constructing checking sequences

    Page(s): 141 - 144
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    An efficient method for constructing checking sequences for strongly connected reduced, synchronous, completely specified, deterministic, sequential machines processing linking homing sequences (LHS) has been described. For machines not possessing an LHS, the only method for constructing a checking sequence requires the use of locating sequences which are often very long. In this correspondence a general method for constructing efficient checking sequences using multiple linking boming sequences instead of locating sequences is presented. View full abstract»

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  • Bit steering in the minimization of control memory in microprogrammed digital computers

    Page(s): 144 - 147
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    Presents an algorithm for microprogram control memory width minimization with the bit steering technique. The necessary and sufficient conditions to detect the steerability of two mutually exclusive sets of microcommands are established. The algorithm encodes the microcommands of the sets with a bit steering common part and also extends the theory to multiple (more than two) sets of microcommands. View full abstract»

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  • Comments on “algorithms for reporting and counting geometric intersections”

    Page(s): 147 - 148
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    Comments on the paper by Bentley and Ottman (ibid., vol.28, p.643-7, 1979) which presents an algorithm for reporting all K intersections among N planar line segments in 0((N+K) log N) time and 0(N+K) storage. With a small modification that storage requirement can be reduced to 0(N) with no increase in computational time, which is important because K can grow as 0(N2). View full abstract»

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  • Control memory word width optimization using multiple-valued circuits

    Page(s): 148 - 153
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    The optimization of read-only memory (ROM) digit dimension for microprogrammed digital computers is considered. The design of integrated injection logic (I2L) multiple valued ROMs is reviewed and designs for corresponding digit-line decoders are presented. Results are presented for determining microoperation groupings that achieve the lower bound digit dimension for multivalued encodings, thus extending to arbitrary radix the theory for the binary case. To illustrate the applicability of these results, the microprogram specifications for previously published optimization examples, as well as that for the Digital Equipment Corporation EDP-9, are shown to have optimal encodings using either three- or four-valued ROMs and either ternary- or quaternary-to-binary decoders, resulting in dramatic savings in device count for the control memory portion of the corresponding machine. View full abstract»

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  • Efficient sorting with CCD's and magnetic bubble memories

    Page(s): 153 - 157
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    The use of sorting in various computer-related applications such as database management, is well established. Normally, sorting is implemented by employing a combination of hardware and software techniques. In this correspondence the authors examine the utility of serial-shifting nature of the charge coupled device (CCD) and the magnetic bubble memories for achieving low-cost sorting within the secondary storage. The radix-sort method has been found to be very suitable for this purpose. Five different memory organizations implementing radix sort have been described in detail and their relative merits are also outlined. View full abstract»

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  • Comments on “the buffer behavior in computer communication systems”

    Page(s): 157
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    Heines1 recently analyzed the buffer behavior in computer communication system under: 1) Poisson arrivals, 2) periodic opportunities for service, 3) random blocking of service, and 4) averaging queue length and delay time observed at customer departure times. Heines' analysis revealed a different result to that of Hsu's [1]. This is because the probability distribution of the buffer content derived by Hsu corresponds to the epochs of "end of service intervals," while that in Heines' corresponds to the buffer content just after a customer departure. Using a (recently introduced) discrete state level crossing analysis [2], Heines' result can be derived from that of Hsu's. The intent of this letter, however, is to point out an alternate viewpoint of this model and to relate Heines' result to some previously published results. It was observed by Heines that if a data packet arrives when the system is idle, service to this data packet may be attempted only at the end of that service interval. This phenomenon may be interpreted as follows: every time the buffer becomes empty the output channel is closed for a length of a slot time. If no data packet arrives during this slot time, the channel is once again closed down for the following slot time. This is continued until at least one data packet arrives. Then the channel will be opened for service at the end of the slot time following the data packet arrival. This model is indeed an M/G/1 queue with geometric service times and "multiple server vacations." The results for this M/G/1 are easily obtained from that of Welch's [3] and are available in [4] and [5]. Using a straightforward translation of the results in [4] and [5] we get the Laplace Stieltjes transform W(s) of the waiting time distribution for this model as (see [6]) \tilde{W}(s) = {(f-\lambda ) \exp (-s) (1- \exp (-s)) \over (\lambda - s + sf) \exp (-s)-(\lambda - s)}, \quad \Re (s) > 0 where f - = Pr {channel available during a slot time} and λ is the data packet arrival rate. Now one may use this viewpoint of this model and the level crossing analysis discussed in [5] to extent this model to accomodate bulk arrival with multitype of customers. View full abstract»

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  • Structure specification with a procedural hardware description language

    Page(s): 157 - 161
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    Describes the extension and formalization of the hardware description language AHPI to form AHPL III. This language provides for nesting AHPL descriptions within descriptions. It incorporates a general index extension mechanism which permits the efficient representation of sets of duplicate descriptions of any complexity. Three types of structures, procedural structures, functional registers, and combinational logic units are permitted. Procedural structures may be primitive or nonprimitive. All but primitive procedural structures share a common syntax. Nesting, declaration, and invocation rules for these distinct structures are specified in a semantics table. View full abstract»

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  • Synchronization and voting

    Page(s): 161 - 164
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    This is an elaboration of the paper `Synchronization and matching in redundant systems' by Davies and Wakerly (ibid., vol.27, p.531-9, 1978). The design of voters for synchronization is strongly dependent on the signaling convention used. This correspondence presents voter designs for three different signaling conventions (transition, level, and pulse). The issue of improved voter performance is also addressed. View full abstract»

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  • The topology of cellular partitioning networks

    Page(s): 164 - 168
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    Investigates generalizations of triangular permuting networks in two directions: the connecting power of cells and the network topology. The main result indicates that permuting, coupling, and partitioning capabilities can be obtained by using 2-, 3-, and 4-state cells, respectively, in a large class of network topologies. View full abstract»

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  • Call for papers

    Page(s): 1
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    Freely Available from IEEE
  • Planned special issues

    Page(s): 1
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    Freely Available from IEEE

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Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
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