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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1981

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Displaying Results 1 - 18 of 18
  • LSI logic testing — An overview

    Page(s): 1 - 17
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    The development of large scale integration (LSI) testing is reviewed. The paper concentrates on the testing of logic components and presents in-depth discussions of the methods of fault modeling, test pattern generation, fault simulation, and design for testability. It is shown how these methods are used in the design of components and how they can be used in support of design automation. Finally, a brief account of test equipment and test data preparation is given. View full abstract»

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  • Counting sequences

    Page(s): 17 - 23
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    A Gray sequence is a counter sequence where the Hamming distance between successive states is one. A construction for any fixed odd distance between successive states is given based on error-correcting codes. Such sequences could be used in testing and fault diagnosis when sequencing through all possible input combinations. Sequences with the maximum possible difference between successive states, alternately n and n-1, are given. A characterization of such maximal change sequences is given. The most nearly uniform even difference sequences are described. The distribution of bit changes or transition counts for individual variables for a counting sequence is considered. View full abstract»

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  • Instruction set processor specifications (ISPS): The notation and its applications

    Page(s): 24 - 40
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    The Instruction Set Processor Specifications (ISPS) computer description language is an evolutionary step towards the formalization of the digital design process at the higher or behavioral levels. It has been used as a design tool, which covers a wider area of application than any other hardware description language. Thus, besides simulation and synthesis of hardware, software generation program verification, and architecture evaluation and control are among the current applications based on ISPS. The range of current and contemplated application areas are proof of the usefulness of the notation and its extension mechanisms. ISPS supports a wide range of applications, rather than a wide range of design levels. Thus, this paper is divided into two parts. The first part describes the notation, its intended use, and the extension mechanisms which allow multiple applications or areas of research to co-exit and share machine descriptions. The second part describes some of the current applications for ISPS. View full abstract»

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  • The edge flag algorithm — A fill method for raster scan displays

    Page(s): 41 - 48
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    Contour (polygon) filling is a primitive required in many application areas of raster scan graphics. The bit-map memory in a frame-store display is computationally well suited to this task, as it provides a large scratch pad working space. In this paper, a number of contour filling algorithms based on the read/write properties of the frame-store memory are compared with the classical `ordered-edge-list' approach. Performance is evaluated on a microcomputer controlled frame-store display system in terms of ability to fill correctly, execution speed and processor memory requirements. A new algorithm, based on a more exact definition of an object edge, is presented. This algorithm, denoted edge flag algorithm, is implemented within the frame-store memory. It features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation. View full abstract»

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  • Measuring designer performance to verify design automation systems

    Page(s): 48 - 61
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    Design automation at the register transfer level of design is still in its infancy, and it is not yet completely understood what the appropriate measures used in direction the automated design process should be. To establish these measures, results of these design automation systems must be compared with some near optimal designs. A set of statistically based experiments is developed to estimate near optimal designs. A method is demonstrated for gathering data on designer performance, specifically at the different levels of systems design, and in general for calibration of other design automation systems where the intuitive designer still performs more capably than the present design algorithms. An analysis of variance is used to indicate the relative importance of various decisions in a system design. It is shown that the algorithm to be implemented and the hardware design style account for 90 percent of the variation in the results. Thus, selecting the design style (e.g., distributed, microprocessor, pipelined, etc.) is the most important parameter for a design automation system. View full abstract»

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  • One-dimensional optimization on multiprocessor systems

    Page(s): 61 - 66
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    This paper presents a straightforward approach to determining how best to utilize an MIMD multiprocessor in the solution of one-dimensional optimization problems involving continuous unimodal functions and nongradient search techniques. A methodology is presented which allows one to consider a variety of speedup functions which may occur in parallel function and systems evaluation. It is shown how the best of two parallel optimization strategies can be determined for a given accuracy, number of processors, and speedup function. View full abstract»

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  • On structured digraphs and program testing

    Page(s): 67 - 77
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    Certain graph theoretic problems dealing with the testing of structured programs are treated. A structured digraph is a digraph that represents a structured program. A labelling procedure which characterizes structured digraphs is described. An efficient algorithm for finding a minimum path cover for the vertices of digraphs that belong to an important family of structured digraphs is given. To model interactions among code segments the notions of `required pairs' and `must pairs' are introduced and the corresponding constrained path cover problems are shown to be NP-complete even for acyclic structured digraphs. View full abstract»

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  • Comments on “revision of the buffer length derivation for a modified Ek/D/1 system by Maritsas and Hartley”

    Page(s): 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    An eight-transistor static logic gate has been designed, which generates the functions OR, NOR, AND, NAND, XOR, and XNOR of two logic variables, under the dynamic control of two programming variables. In addition to its versatility as a building block, the dynamic programmability of the gate makes it a powerful tool for the efficient design of complex digital networks. View full abstract»

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  • Design of a dynamically programmable logic gate

    Page(s): 79 - 81
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    An eight-transistor static logic gate has been designed, which generates the functions OR, NOR, and, nand, xor, and XNOR of two logic variables, under the dynamic control of two programming variables. In addition to its versatility as a building block, the dynamic programmability of the gate makes it a powerful tool for the efficient design of complex digital networks. View full abstract»

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  • A fault diagnosis algorithm for asymmetric modular architectures

    Page(s): 81 - 83
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    Pertains to the analysis of an algorithm for the automatic fault diagnosis of asymmetric modular networks. View full abstract»

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  • Observations concerning the complexity of a class of on-line algebraic problems

    Page(s): 83 - 86
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    Defines and studies a class of on-line algebraic problems; a particular problem in this class is specified by providing an n×n matrix A. The author shows that the question of algebraic complexity reduces to determining the existence of what he calls (r, u) factorizations of A. Given an n×n matrix A, a factorization A =RU (R and U are n×m and m×n matrices, respectively; m unconstrained) is called an (r, u) factorization, provided that no row of R has more than r nonzero entries and no column of U has more than u nonzero entries. The existence of (r, u) factorization is explored from a general perspective. View full abstract»

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  • Correction to “complete solution of boolean equations”

    Page(s): 87
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    The following errors should be noted in the above correspondence.1 View full abstract»

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  • Correction to “distributed enumeration on between computers”

    Page(s): 87
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    Due to a production error in the September 1980 issue of this Transactions, the title of the above paper1 was incorrectly printed on p. 818. It should read View full abstract»

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  • [Advertisements]

    Page(s): 1
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  • IEEE copyright form

    Page(s): 1 - 2
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  • Announcement & call for papers

    Page(s): 1
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  • Call for papers

    Page(s): 1
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org