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IEEE Design & Test of Computers

Issue 4 • Date Dec. 1993

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Displaying Results 1 - 7 of 7
  • Trends in silicon-on-silicon multichip modules

    Publication Year: 1993, Page(s):8 - 17
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1205 KB)

    Three example applications of silicon-on-silicon multichip modules are discussed: a module used in a parallel processor, a low-cost silicon module for a high-volume consumer product application, and a high-performance digital telecommunications module. These applications illustrate the changes occurring in this technology and the forces that are driving these changes.<> View full abstract»

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  • SURF: rubber-band routing system for multichip modules

    Publication Year: 1993, Page(s):18 - 26
    Cited by:  Papers (25)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1039 KB)

    Current PCB (printed circuit board)-based routing tools cannot meet the performance and cost constraints presented by today's packaging technologies, including thin-film multichip modules. The authors describe SURF, a routing system designed specifically to meet these challenges. The strength of the SURF system comes from its extremely flexible rubber-band data representation. The rubber-band mode... View full abstract»

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  • High-performance MCM routing

    Publication Year: 1993, Page(s):27 - 37
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1204 KB)

    The authors describe the multilayer MCM (multichip module) routing problem, and propose an approach for routing high-performance MCMs with the objective of minimizing interconnect delays and crosstalk. They first introduce an approach for rapidly estimating the time-domain response of lossy transmission line trees, and propose a realistic second-order delay model for MCM interconnects. The delay m... View full abstract»

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  • A new framework for designing: built-in test multichip modules with pipelined test strategy

    Publication Year: 1993, Page(s):38 - 51
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1316 KB)

    A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and t... View full abstract»

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  • Design issues in parallel simulation languages

    Publication Year: 1993, Page(s):52 - 63
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1397 KB)

    The authors address several key issues in designing languages for parallel discrete-event simulation and survey the state-of-the-art techniques aimed at solving these problems. Attention is given to issues that are specific to parallel simulation, e.g., the parallel synchronization schemes, or issues that have not previously been a problem for sequential simulation, e.g., termination. Various spec... View full abstract»

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  • Hardware-software cosynthesis for microcontrollers

    Publication Year: 1993, Page(s):64 - 75
    Cited by:  Papers (332)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1145 KB)

    The authors present a software-oriented approach to hardware-software partitioning which avoids restrictions on the software semantics as well as an iterative partitioning process based on hardware extraction controlled by a cost function. This process is used in Cosyma, an experimental cosynthesis system for embedded controllers. As an example, the extraction of coprocessors for loops is demonstr... View full abstract»

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  • A fault-tolerant digital artificial neuron

    Publication Year: 1993, Page(s):76 - 82
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (607 KB)

    A simple fault-tolerant digital artificial neuron is introduced. Two digital implementations based on two different adders are examined. Reliability, fault coverage, and hardware redundancy analyses are carried out to characterize the proposed fault-tolerant digital neural module. These analyses reveal that, for a 114% increase in hardware, a 92.07% fault detection coverage and a 21.15% fault reco... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty