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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 2012

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Displaying Results 1 - 25 of 53
  • Table of contents

    Publication Year: 2012 , Page(s): C1 - 2562
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2012 , Page(s): C2
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  • EDS Publication Policy on Manuscript Transfer Among Its Flagship Publications

    Publication Year: 2012 , Page(s): 2563
    Cited by:  Papers (2)
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  • Prepublication Policy for Submissions to IEEE Transactions on Electron Devices

    Publication Year: 2012 , Page(s): 2564 - 2565
    Cited by:  Papers (2)
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  • Changes in the Editorial Board

    Publication Year: 2012 , Page(s): 2566
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  • Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket

    Publication Year: 2012 , Page(s): 2567 - 2574
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications. View full abstract»

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  • Read-Preferred SRAM Cell With Write-Assist Circuit Using Back-Gate ETSOI Transistors in 22-nm Technology

    Publication Year: 2012 , Page(s): 2575 - 2581
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (782 KB) |  | HTML iconHTML  

    The degradation of the read stability and write ability of static random-access memory (SRAM) is becoming a critical problem in deep submicrometer technology. To solve this problem, there are many SRAM cell design options such as preferred cells and assist circuits. In addition, extremely thin silicon-on-insulator (ETSOI) with a buried oxide offers an independent back-gate control. In this paper, previously proposed SRAM back-gate-assist circuit schemes are analyzed. From this, we propose a read-preferred SRAM cell with a write-assist circuit using the back-gate ETSOI. The proposed write-assist circuit minimizes the dynamic power overhead and satisfies a sufficient cell sigma in all cells during the read and write operations. View full abstract»

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  • Effects of Small Geometries on the Performance of Gate First High- \kappa Metal Gate NMOS Transistors

    Publication Year: 2012 , Page(s): 2582 - 2588
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    This paper discusses in detail the effect of small geometries on the performance of NMOS transistors fabricated using a 28-nm gate-first CMOS technology. It is shown that the threshold voltage and transconductance of the NMOS transistors increase with the decrease in the channel width, and this effect is enhanced at shorter gate lengths. PMOS transistors show conventional width dependence. The possible physical mechanisms responsible for this anomalous behavior are identified and explained through detailed measurements. A 2-D charge-distribution-based model is proposed to model this anomalous effect. The accuracy of the proposed model is verified by comparing it with the experimental and simulated data. View full abstract»

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  • Accurate Calculation of Gate Tunneling Current in Double-Gate and Single-Gate SOI MOSFETs Through Gate Dielectric Stacks

    Publication Year: 2012 , Page(s): 2589 - 2596
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1370 KB) |  | HTML iconHTML  

    Recently, a new generation of MOSFETs, called multigate transistors, has emerged with geometries that will allow the downscaling and continuing enhancement of computer performance into next decade. The low dimensions in these nanoscale transistors exhibit increasing quantum effects, which are no longer negligible. Gate tunneling current is one of such effects that should be efficiently modeled. In this paper, an accurate description of tunneling in ultrathin body double-gate and single-gate MOSFET devices through layers of high- κ dielectrics, which relies on the precise determination of quasi-bound states, is developed. For this purpose, the perfectly matched layer method is embedded in each iteration of a 1-D Schrödinger-Poisson solver by introducing a complex stretched coordinate which allows applying artificial absorbing layers in the boundaries. View full abstract»

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  • Threshold Voltage Variability of NROM Memories After Exposure to Ionizing Radiation

    Publication Year: 2012 , Page(s): 2597 - 2602
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (769 KB) |  | HTML iconHTML  

    Threshold voltage (Vth) behavior of nitride read-only memories (NROMs) was studied after irradiation with photons (γ- and X-rays), light and heavy ions. Both programmed and nonprogrammed single cells were investigated. The data suggest that two main physical phenomena are contributing to Vth variation and that the Vth loss and the variability can be modeled by a Weibull statistics with a shape parameter k ~ 2.2 regardless of the irradiation species and total dose. The same peculiarities were found in large memory arrays, confirming the results from single-cell studies but with significantly larger statistics. Hence, once the irradiation dose is known, the Vth loss distribution can be obtained, thus providing a predictive model of the radiation tolerance of NROM memory arrays. View full abstract»

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  • NBTI in n-Type SOI Access FinFETs in SRAMs and Its Impact on Cell Stability and Performance

    Publication Year: 2012 , Page(s): 2603 - 2609
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB) |  | HTML iconHTML  

    We identify the possibility of negative-bias temperature instability (NBTI) in n-type silicon-on-insulator (SOI) FinFETs used as access transistors in SRAMs. We discuss that in the hold state of the SRAM cell, one of the access transistors may operate in the accumulation region and experience NBTI degradation. We compare NBTI in p- and n-type SOI FinFETs and show that NBTI in n-FinFETs affects only a part of the channel due to the presence of n+ source/drain regions. Worst case analysis of the joint effect of NBTI in access and pull-up FinFETs on cell stability and performance of 6T SRAMs is carried out and compared with the conventional approach of considering NBTI in pull-up FinFETs only. View full abstract»

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  • High-Frequency Ballistic Transport Phenomena in Schottky Barrier CNTFETs

    Publication Year: 2012 , Page(s): 2610 - 2618
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (703 KB) |  | HTML iconHTML  

    The effective-mass Schrödinger equation is solved directly for the wave functions to explore the steady state and the time-dependent quantum-ballistic transport in Schottky barrier carbon nanotube (CNT) field-effect transistors (FETs). The employed contact parameters allow for discontinuities of the effective mass at the metal-CNT interface, and carefully chosen boundary conditions minimize spurious reflections at the simulation domain boundaries. Two-port Y-parameters of a selected device structure are computed and qualitatively explained with the time dependence of coherent quantum-ballistic charge injection. The finite escape times of the charge carriers in an open quantum system are identified for determining the inertial response to high-frequency terminal signals. Since the escape times depend on the shape of the Schottky barriers, the latter contribute to the dynamic behavior of ballistic CNTFETs. View full abstract»

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  • A Scalable Electrothermal Model for Transient Self-Heating Effects in Trench-Isolated SiGe HBTs

    Publication Year: 2012 , Page(s): 2619 - 2625
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (975 KB) |  | HTML iconHTML  

    This paper demonstrates a scalable electrothermal model for transient self-heating effects in trench-isolated SiGe heterojunction bipolar transistors (HBTs). The scalability of the thermal model has been investigated by considering pyramidal heat diffusion approximation between the heat source and the thermal ground. Three-dimensional thermal TCAD simulations have been carried out to obtain transient variations of the junction temperature and to extract the thermal impedance in the frequency domain. A recursive thermal network with scalable model parameters has been developed and added at the temperature node of the HBT compact model HiCuM. This network has been verified through numerical simulations and by low-frequency s-parameter measurements and found to be in excellent agreement for various device geometries. View full abstract»

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  • Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology

    Publication Year: 2012 , Page(s): 2626 - 2634
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1189 KB) |  | HTML iconHTML  

    An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias. View full abstract»

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  • DC Compact Model for SOI Tunnel Field-Effect Transistors

    Publication Year: 2012 , Page(s): 2635 - 2642
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (958 KB) |  | HTML iconHTML  

    A physics-based dc compact model for SOI tunnel field-effect transistors (TFETs) has been developed in this paper utilizing Landauer approach. The important transistor electrical parameters, i.e., threshold voltage Vth, charge in the channel Q, gate capacitance CG, drain current IDS, subthreshold swing S, transconductance gm, and output conductance gDS, have been modeled. The model predicts the low subthreshold swing values (less than 60 mV/dec) observed in TFETs and shows a good match with the technology computer aided design (TCAD) results. Model validation was carried out using TCAD simulation for different TFET structures with abrupt junctions, i.e., 40-nm Si nTFET and pTFET, a 0.4-μm Si nTFET, and a 40-nm Ge nTFET. The compact model predictions are in good agreement with the TCAD simulation results. View full abstract»

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  • Equivalent Circuit Model for a GaN Gate Injection Transistor Bidirectional Switch

    Publication Year: 2012 , Page(s): 2643 - 2649
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    The switching waveforms and losses of a GaN gate injection transistor (GIT) bidirectional switch, a type of four-terminal device, were analyzed for the first time using an equivalent circuit model. By applying a three-terminal model to the equivalent circuit model of the GIT bidirectional switch and by using the waveforms of the chopper circuit, the parameters were derived with high accuracy. Furthermore, gate resistance dependence was added to the input capacitance component connected to the gate terminal in order to contain the influence of the gate structure of the GIT. It was confirmed that the calculated switching waveforms and losses agree well with those of the experimental values with over 90% accuracy, even in cases where circuit conditions for circuit voltage, load current, and gate resistance were varied. View full abstract»

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  • AlGaN/GaN MOSHEMT With High-Quality \hbox {Gate} \hbox {SiO}_{2} Achieved by Room-Temperature Radio Frequency Magnetron Sputtering

    Publication Year: 2012 , Page(s): 2650 - 2655
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (892 KB) |  | HTML iconHTML  

    High-quality SiO2 is deposited on GaN by radio frequency (RF) magnetron sputtering at room temperature. Adding oxygen to the sputtering gas effectively compensated for the oxygen vacancies and resulted in a breakdown field of 9.6 MV/cm for the sputtered- SiO2 film on GaN. The reduced electron concentration and mobility of the 2-D electron gas due to the sputtering-induced surface damage were effectively removed by an optimized postannealing treatment. A sputtered-SiO2/ AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (HEMT) (MOSHEMT) was demonstrated with the lowest thermal energy requirement among all the dielectric deposition techniques, which exhibited a saturation drain current of 621 mA/mm and a breakdown voltage of 205 V at the gate-drain distance of 2 μm. More than four orders of magnitude lower gate leakage current than conventional HEMT of the same dimension was achieved. These characteristics demonstrate excellent potential of using RF magnetron sputtering to produce gate insulators for GaN-based MOSHEMTs. View full abstract»

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  • Quantitative Analysis of Initial Short-Term Aging Behavior and Its Implication for the Efficiency Droop in Blue Light-Emitting Diodes

    Publication Year: 2012 , Page(s): 2656 - 2661
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (963 KB) |  | HTML iconHTML  

    We have quantitatively analyzed the short-term aging behavior of blue light-emitting diodes using the current-component analysis method. The internal quantum efficiency and luminescence output decrease monotonically with the aging time and are stabilized at low operation current, owing to the increase and subsequent stabilization in the tunneling and nonradiative currents, while they show complicated behavior at high operation current due to the interplay of different changing rates in the radiative and nonradiative recombination current components. The current-component analysis enables both the quantitative understanding of the aging behavior and the identification of the aging mechanisms. Also shown is that the loss current, which is responsible for the efficiency droop, is approximately proportional to the cube of the injected carrier concentration. This suggests that the origin of the efficiency droop is a three-carrier process. View full abstract»

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  • Capacitance Modeling and Characterization of Planar MOSCAP Devices for Wideband-Gap Semiconductors With High- \kappa Dielectrics

    Publication Year: 2012 , Page(s): 2662 - 2666
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (215 KB) |  | HTML iconHTML  

    This paper presents a capacitance model and mobility extraction method through the use of tapered transmission line theory for accumulation-mode MOSCAP test structures. The analytical model accounts for the discrepancies commonly found when measuring the capacitance of nontraditional MOSCAP architectures. Through fabrication of a planar MOSCAP, this model accurately reproduced consistent capacitance density measurements for several device dimensions and high-κ dielectric thicknesses. In this paper, the theoretical basis of the model extracts the effective electron mobility of the accumulation channel in the semiconductor without fabricating a transistor. View full abstract»

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  • Strain and Temperature Dependence of Defect Formation at AlGaN/GaN High-Electron-Mobility Transistors on a Nanometer Scale

    Publication Year: 2012 , Page(s): 2667 - 2674
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1459 KB) |  | HTML iconHTML  

    We use depth-resolved cathodoluminescence spectroscopy (DRCLS), Kelvin probe force microscopy (KPFM), and surface photovoltage spectroscopy (SPS) on a nanometer scale to map the temperature, strain, and defects inside GaN high-electron-mobility transistors. DRCLS maps temperature at localized depths, particularly within the 2-D electron gas region during device operation. KPFM maps surface electric potential across the device, revealing lower potential patches that decrease rapidly with increasing off-state stress. CL spectra acquired at these patches exhibit defect emissions that increase with both on- and off-state stresses and that increase with decreasing surface potential. SPS also reveals features of deep level gap states generated after device operation that reduce near-band-edge emission and increase surface band bending. Our nanoscale measurements are consistent with defect generation by inverse piezoelectric field-induced stress at the gate edge on the drain side at high voltage. View full abstract»

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  • Analysis of Dynamic Range, Linearity, and Noise of a Pulse-Frequency Modulation Pixel

    Publication Year: 2012 , Page(s): 2675 - 2681
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (806 KB) |  | HTML iconHTML  

    A complete pulse-frequency modulation (PFM) pixel design analysis and noise measurement for CMOS image sensor applications are presented. This work investigates the design parameters such as dynamic range (DR), signal linearity, and comparator characteristics. The design strategies for wide DR imaging are addressed in detail, and signal linearity is analyzed by considering the analog circuit parameters. The temporal noise is also measured to understand the design tradeoffs of the PFM pixels. The analysis is executed by performing HSPICE simulation and practical pixel measurements. The technology used by the measured pixel is a 0.18-μm one-poly six-metal CMOS process. According to the results, a PFM pixel using the submicrometer CMOS process has a DR of 130-160 dB, and the cost of reaching a higher signal linearity or lower noise floor is the loss of frame rate. In addition, the bandwidth of the comparator can be extended to improve sensor linearity. View full abstract»

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  • Effect of the Driving Waveform With Negative-Going Ramp on the Address Discharge Characteristics of Plasma Display Panel With High-Gamma Cathode Material

    Publication Year: 2012 , Page(s): 2682 - 2688
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (902 KB) |  | HTML iconHTML  

    The address discharge characteristics of the plasma display with a MgO single cathode layer and the one with a MgO-SrO double cathode layer were investigated. In particular, the conventional waveform with a positive-going ramp and the proposed waveform with a negative-going ramp were applied in order to demonstrate that the polarity of the scan electrode during the reset period affects the dynamic voltage margin and the address discharge time lag. It was confirmed that the total address discharge time lag of the plasma display with the MgO-SrO double cathode layer decreased by about 550 ns by applying the proposed waveform with the negative-going ramp. View full abstract»

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  • Amorphous InGaZnO Thin-Film Transistors—Part I: Complete Extraction of Density of States Over the Full Subband-Gap Energy Range

    Publication Year: 2012 , Page(s): 2689 - 2698
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2867 KB) |  | HTML iconHTML  

    A combination of the multifrequency C- V and the generation-recombination current spectroscopy is proposed for a complete extraction of density of states (DOS) in amorphous InGaZnO thin-film transistors (a-IGZO TFTs) over the full subband-gap energy range (EVEEC) including the interface trap density between the gate oxide and the a-IGZO active layer. In particular, our result on the separate extraction of acceptor- and donor-like DOS is noticeable for a systematic design of amorphous oxide semiconductor TFTs because the former determines their dc characteristics and the latter does their threshold voltage (VT) instability under practical operation conditions. The proposed approach can be used to optimize the fabrication process of thin-film materials with high mobility and stability for mass-production-level amorphous oxide semiconductor TFTs. View full abstract»

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  • Amorphous InGaZnO Thin-Film Transistors—Part II: Modeling and Simulation of Negative Bias Illumination Stress-Induced Instability

    Publication Year: 2012 , Page(s): 2699 - 2706
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1285 KB) |  | HTML iconHTML  

    Based on the physical model of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) and the extracted density of states described in Part I, a quantitative investigation of mechanisms on the negative bias illumination stress (NBIS)-induced threshold voltage VT instability of a-IGZO TFTs is presented. It is found that the shallow donor state-creation model explains the NBIS time evolution of the electrical characteristics very well. Furthermore, the semi-empirical rule of the NBIS-induced ΔVT is proposed and demonstrated based on the shallow donor state-creation model. The proposed approach can be used to optimize the fabrication process and to explore high-performance thin-film materials for mass-production-level amorphous oxide semiconductor TFTs to be innovatively used in the near future. View full abstract»

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  • High-Efficiency Silicon Photodiode Detector for Sub-keV Electron Microscopy

    Publication Year: 2012 , Page(s): 2707 - 2714
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1203 KB) |  | HTML iconHTML  

    A silicon photodiode detector is presented for use in scanning electron microscopy (SEM). Enhanced imaging capabilities are achieved for sub-keV electron energy values by employing a pure boron (PureB) layer photodiode technology to deposit nanometer-thin photosensitive anodes. As a result, imaging using backscattered electrons is demonstrated for 50-eV electron landing energy values. The detector is built up of several closely packed photodiodes, and to obtain high scanning speed, each photodiode is engineered with low series resistance and low capacitance values. The low capacitance (<; 3 pF/mm2) is facilitated by thick, almost intrinsically-doped epitaxial layers grown to achieve the necessarily wide depletion regions. For the low series resistance, diode metallization has been patterned into a conductive grid directly on top of the nanometer-thin PureB-layer front-entrance window. Finally, a through-wafer aperture in the middle of the detector is micromachined for flexible positioning in the SEM system. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego