IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Oct. 2012

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  • Table of contents

    Publication Year: 2012, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2012, Page(s): C2
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  • Energy-Efficient Datacenters

    Publication Year: 2012, Page(s):1465 - 1484
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1507 KB) | HTML iconHTML

    Pervasive use of cloud computing and the resulting rise in the number of datacenters and hosting centers (that provide platform or software services to clients who do not have the means to set up and operate their own computing facilities) have brought forth many concerns, including the electrical energy cost, peak power dissipation, cooling, and carbon emission. With power consumption becoming an... View full abstract»

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  • Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics

    Publication Year: 2012, Page(s):1485 - 1498
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3442 KB) | HTML iconHTML

    Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. In this paper, we advance a novel optimization strategy that explicitly handles the error of the model in the course of... View full abstract»

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  • Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis

    Publication Year: 2012, Page(s):1499 - 1507
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3282 KB) | HTML iconHTML

    This paper describes an original computational procedure to extract the perturbation projection vector of oscillators by means of a frequency domain technique. A key feature of the method is that it relies on the periodic transfer function analysis, which is available in most circuit simulators, and thus it can easily be exploited by oscillator designers. The accuracy of the proposed extraction pr... View full abstract»

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  • synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs

    Publication Year: 2012, Page(s):1508 - 1521
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4443 KB) | HTML iconHTML

    This paper presents a high-level synthesis framework called synASM that synthesizes abstract state machines (ASMs) to VHDL for field-programmable gate arrays (FPGAs). In particular, this paper focuses on the specification, scheduling, and synthesis of parallel and timed constructs. ASMs possess well-defined formal semantics for sequential and parallel computation, and their composition. We extend ... View full abstract»

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  • Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning

    Publication Year: 2012, Page(s):1522 - 1535
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8161 KB) | HTML iconHTML

    A parallel transient simulation technique for multiphysics circuits is presented. The technique develops partitions utilizing the inherent delay present within a circuit and between physical domains. A state-variable-based circuit delay element is presented, which implements the coupling between two spatially or temporally isolated circuit partitions. A parallel delay-based iterative approach for ... View full abstract»

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  • Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

    Publication Year: 2012, Page(s):1536 - 1545
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5601 KB) | HTML iconHTML

    In this paper, a new efficient and accurate analytical eye-diagram determination technique for interconnect lines is presented. The simplest input test signal model for the intersymbol interference analysis of high-speed data links is mathematically formulated. Since input test patterns for eye boundaries are determined analytically, it is considered very convenient and efficient. The proposed tec... View full abstract»

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  • A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations

    Publication Year: 2012, Page(s):1546 - 1557
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9880 KB) | HTML iconHTML

    This paper introduces a novel distributed algorithm for performing the layout geometry operations usually found in design rule checking, layout verification, and mask synthesis. A large number of machines are typically available to the user during the mask synthesis flow. As multiple machines or cores become more ubiquitous, even designers using layout verification tools will have access to a larg... View full abstract»

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  • Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs

    Publication Year: 2012, Page(s):1558 - 1571
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2960 KB) | HTML iconHTML

    It is becoming increasingly important to design high-performance circuits with as low power as possible. In this paper, we study the gate sizing and device parameter selection problem for today's industrial designs. We first outline the typical practical problems that make it difficult to use traditional algorithms on high-performance industrial designs. Then, we propose a Lagrangian relaxation-ba... View full abstract»

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  • Model-Based Virtual Prototype Acceleration

    Publication Year: 2012, Page(s):1572 - 1585
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3294 KB) | HTML iconHTML

    Today, virtual prototypes are often employed for software development early in the design flow. There, high simulation speed may support fast development. So, the acceleration of virtual prototype simulation is important in the early phases of design. To accelerate virtual prototypes, complex prototype simulation can be prevented by exploiting model-specific knowledge. We replace complex event-dri... View full abstract»

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  • Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory

    Publication Year: 2012, Page(s):1586 - 1599
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6214 KB) | HTML iconHTML

    Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases-suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and t... View full abstract»

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  • Built-In Self-Repair Scheme for the TSVs in 3-D ICs

    Publication Year: 2012, Page(s):1600 - 1613
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8725 KB) | HTML iconHTML

    3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of ... View full abstract»

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  • Improving Diagnosis Through Failing Behavior Identification

    Publication Year: 2012, Page(s):1614 - 1625
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2457 KB) | HTML iconHTML

    Logic diagnosis analyzes the observed failing circuit responses to derive the potential defect sites. This paper describes a method for improving diagnosis through failing behavior identification (FBI). FBI captures defect behavior (i.e., activation conditions of the defect) by identifying the signal lines related to defect activation. This additional information allows the root cause to be estima... View full abstract»

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  • IEEE Xplore Digital Library [advertisement]

    Publication Year: 2012, Page(s): 1626
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  • IEEE Copyright Form

    Publication Year: 2012, Page(s):1627 - 1628
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2012, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2012, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu