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Embedded Systems Letters, IEEE

Issue 3 • Date Sept. 2012

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Displaying Results 1 - 13 of 13
  • Table of contents

    Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Page(s): C2
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  • HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design

    Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (798 KB) |  | HTML iconHTML  

    Differential power analysis (DPA) attacks find the correlation between power consumption and secret data in crypto-hardware. This letter proposes homogeneous dual-rail logic (HDRL), a standard cell DPA attack countermeasure that theoretically guarantees fully balanced power consumption and significantly improves DPA attack resistivity. Our experimental results on the AES S-Box circuit show that HDRL successfully prevents DPA attacks in all cases. View full abstract»

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  • Scheduling of Accuracy-Constrained Real-Time Systems in Dynamic Environments

    Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (514 KB) |  | HTML iconHTML  

    Many real-time embedded systems are sensitive to both the accuracy and timeliness of job results. In this letter, two sources of inaccuracy are considered for such systems: 1) input data noise (IDN) due to the environmental transient noises, and 2) age of data (AD) related to the time of capturing data, which may depend on the length of time between capturing and using the input data. Thus, in the presence of one or more jobs in the system, some tradeoffs are needed among capturing data with an appropriate IDN when the environment is less noisy, reducing AD, and respecting the timeliness of jobs. Our emphasis in the current study is to model firm real-time jobs having some thresholds for the inaccuracy and handle the aforementioned tradeoff by the system scheduler. An online accuracy-aware real-time scheduler is also proposed and evaluated. View full abstract»

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  • Optimized Frame Packing for Embedded Systems

    Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (613 KB) |  | HTML iconHTML  

    During system synthesis (i.e., task allocation) the transmission of messages between tasks is usually addressed in a simplistic way. If a message is exchanged via an external bus, it is assumed each message is packed in an individual frame. This assumption leads to an overestimation of bus bandwidth demand and frame response time. For some systems (i.e., automotive), this pessimism is not acceptable and therefore frame packing is often performed where multiple messages are packed into a single frame. In this paper, an improved frame packing approach is provided. View full abstract»

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  • Zebra: Building Efficient Network Message Parsers for Embedded Systems

    Page(s): 69 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    Supporting standard text-based protocols in embedded systems is challenging because of the often limited computational resources that embedded systems provide. To overcome this issue, a promising approach is to build parsers directly in the hardware. Unfortunately, developing such parsers is a daunting task for most developers as it is at the crossroads of several areas of expertise, such as low-level network programming or hardware design. In this letter, we propose Zebra, a generative approach that drastically eases the development of hardware parsers and their use in network applications. To validate our approach, we used Zebra to generate hardware parsers for widely used protocols, including HTTP, SMTP, SIP, and RTSP. Our experiments show that Zebra-based parsers are up to 11 times faster than software-based parsers. View full abstract»

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  • Bandwidth-Sensitivity-Aware Arbitration for FPGAs

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    Field-programmable gate arrays (FPGAs) commonly implement massively parallel circuits that require significant memory bandwidth. Due to I/O and memory limitations, parallel tasks often share bandwidth via arbitration, whose efficiency is critical to ensure parallelism is not wasted. In this letter, we introduce a bandwidth-sensitivity-aware heuristic for arbitration that analyzes the effect of memory bandwidth on performance for each application task, and then accordingly allocates bandwidth to minimize execution time. When compared to round robin (RR) arbitration, application speedups as high as 6.5×are achieved. View full abstract»

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  • Special Issue on Rigorous Modeling and Analysis of Cyber-Physical Systems

    Page(s): 77
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  • Cali for participation - ESWEEK 2012- http://www.esweek.org

    Page(s): 78
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  • IEEE Xplore Digital Library [advertisement]

    Page(s): 79
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  • IEEE Foundation [advertisement]

    Page(s): 80
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  • IEEE Embedded Systems Letters information for authors

    Page(s): C3
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  • [Blank page - back cover]

    Page(s): C4
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Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo