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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 9 • Date Sept. 2012

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Displaying Results 1 - 25 of 28
  • [Front cover]

    Publication Year: 2012 , Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Publication Year: 2012 , Page(s): C2
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  • Table of contents

    Publication Year: 2012 , Page(s): 1405 - 1406
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  • Effects of Sol-Gel Treatment and Plating on the Electrical Properties of Multilayer Filters

    Publication Year: 2012 , Page(s): 1407 - 1411
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1019 KB) |  | HTML iconHTML  

    The effects of sol-gel treatment and plating on the electrical properties of multilayer filters were investigated. The results showed that the sol-gel treatment process can effectively lower the apparent porosity of multilayer filters, preventing the penetration of electroplate liquid into the filters. The mean insertion loss rise for the sol-gel-treated components was 0.171 dB, which increased up to 0.811 dB for the filters without sol-gel seal treatment. Microstructural studies revealed that the sol-gel seal treatment is an effective preplating treatment to diminish the insertion loss of multilayer filters. View full abstract»

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  • Development of Cu/Ni/SnAg Microbump Bonding Processes for Thin Chip-on-Chip Packages Via Wafer-Level Underfill Film

    Publication Year: 2012 , Page(s): 1412 - 1419
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1322 KB) |  | HTML iconHTML  

    3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (μ-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <; 50 μm at the outermost region of the packaging structure without μ-bumps significantly reduces approximately 2 μm of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the st- uctural optimization of packaging assemblies via the WLUF. View full abstract»

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  • Quasi-Axial GRIN Lens Implemented in Wedge-Shaped Fiber Coupling With InP-Based PLC

    Publication Year: 2012 , Page(s): 1420 - 1425
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    A 3-D equivalent rectangle approximation staircase concatenation method to analyze the optical mode evolution in a wedge-shaped fiber (WSF) is proposed in this paper. A scheme with an axial gradient-index (AGRIN) lens between the WSF and InP-based planar lightwave circuit (PLC) chip, yielding higher transmission efficiency than those with two cascaded lenses and one radial GRIN lenses, by 2.282 and 7.816 dB, respectively, is devised and experimentally demonstrated. The WSF-AGRIN-PLC-single-mode fiber coupling linkage supplies a preferable solution for solving the problem of index mismatching in fiber-to-InP-based PLC assembly to achieve a high-efficiency connection. View full abstract»

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  • Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

    Publication Year: 2012 , Page(s): 1426 - 1433
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1561 KB) |  | HTML iconHTML  

    Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization. View full abstract»

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  • Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

    Publication Year: 2012 , Page(s): 1434 - 1441
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1455 KB) |  | HTML iconHTML  

    Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (~30 μm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-μm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and single-bump resistance data. Assembled bump resistivity was found to be ~ 3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections. View full abstract»

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  • Development of a 3-D Process Technology for Wafer-Level Packaging of MEMS Devices

    Publication Year: 2012 , Page(s): 1442 - 1448
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1295 KB) |  | HTML iconHTML  

    This paper presents a simple and low-cost 3-D process technology for the wafer-level packaging (WLP) of microelectromechanical system (MEMS) devices. A small-sized WLP (1.0 × 1.0 × 0.35 mm) with a hermetically sealed cavity for the moving parts of MEMS devices was fabricated by using specially designed processes. The WLP was developed using three key techniques: through-wafer interconnection, wafer bonding, and bilateral face-MEMS fabrication. The expense and complexity of processes such as silicon deep reactive ion etching and electroplating that arise from bilateral processing for through-wafer interconnection were overcome by using bulk micromachining technology. The fabricated WLP chips with a bonding area of 0.314 mm2 showed an average shear strength of 9.74 kg/mm2 and a leak rate less than 7 × 10-10 mbar.cc/sec. In addition, the chips had less than 0.1 dB insertion loss before and after reliability testing. This newly developed 3-D process technology is a good candidate for WLP MEMS fabrication because it is simple and cost-effective. View full abstract»

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  • Study on the Near Field Characteristic of Antenna in Package

    Publication Year: 2012 , Page(s): 1449 - 1454
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    In this paper, the finite difference time domain model for the antenna in package is presented. The distribution of the electric field in the package cavity is analyzed, and a method that reduces the near field is proposed. By arranging via position reasonably, at most the area of the cavity electric field is uniform and decreased less than 10 dBV/m. The measured and simulated results show that the new shielding structure can decrease the electric field in the package cavity by about 10 dBV/m. View full abstract»

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  • Phase Compensation of Cascaded Conductor-Backed CPW Periodic Cells

    Publication Year: 2012 , Page(s): 1455 - 1464
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    Several unit cells of conductor-backed coplanar waveguides with and without loading using thin-film ceramic technology are investigated. The frequency-dependent lumped equivalent circuit values of the cells are extracted from the full-wave electromagnetic analysis. Slow-wave periodic transmission lines and end-coupling bandpass filters (BPFs) are designed, fabricated, and measured. Size reductions of 23% and 27% for the loaded filters and several times increase of inverter values for the coupling inverters are achieved compared to that for the unloaded ones. A systematic design method by using cell cascading with compensation is proposed for the designs of the lines and filters. It is also demonstrated that “finite ground,” used in conductor-backed coplanar waveguides in the literature, is no longer suitable for the end-coupling BPFs due to the leakages. The leakages of finite ground deteriorate the stopband rejection of filters as much as up to 32 dB compared with that of “via ground”. View full abstract»

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  • Modeling and Design Optimization of Ultrathin Vapor Chambers for High Heat Flux Applications

    Publication Year: 2012 , Page(s): 1465 - 1479
    Cited by:  Papers (1)
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    Passive phase-change thermal spreaders, such as vapor chambers have been widely employed to spread the heat from small-scale high-flux heat sources to larger areas. In this paper, a numerical model for ultrathin vapor chambers has been developed, which is suitable for reliable prediction of the operation at high heat fluxes and small scales. The effects of boiling in the wick structure on the thermal performance are modeled, and the model predictions are compared with experiments on custom-fabricated vapor chamber devices. The working fluid for the vapor chamber is water and a condenser side temperature range of 293 K-333 K is considered. The model predictions agree reasonably well with experimental measurements and reveal the input parameters to which thermal resistance and vapor chamber capillary limit are most sensitive. The vapor space in the ultrathin devices offers significant thermal and flow resistances when the vapor core thickness is in the range of 0.2 mm-0.4 mm. The performance of a 1-mm-thick vapor chamber is optimized by studying the variation of thermal resistance and total flow pressure drop as functions of the wick and vapor core thicknesses. The wick thickness is varied from 0.05 to 0.25 mm. Based on the minimization of a performance cost function comprising the device thermal resistance and flow pressure drop, it is concluded that the thinnest wick structures (0.05 mm) are optimal for applications with heat fluxes below 50 W/cm2 , while a moderate wick thickness of 0.1 mm performs best at higher heat flux inputs 50 (>;W/cm2). View full abstract»

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  • Thermal Management of Power Inverter Modules at High Fluxes via Two-Phase Spray Cooling

    Publication Year: 2012 , Page(s): 1480 - 1485
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2142 KB) |  | HTML iconHTML  

    A spray cooling system was developed and tested for thermal management of power inverter modules utilized in automotive applications. The system featured an array of 1×2 pressure atomized nozzles that used 88°C boiling point antifreeze coolant with 0.15-l/min.cm2 liquid flow rate and 145-kPa pressure drop. A 2-cm2 simulated device, having two kinds of enhanced spray surface with microscale structures, reached up to 400-W/cm2 heat flux with as low as 14 °C surface superheat. These experimental results demonstrated the capability of greatly reducing the overall thermal resistance of the inverter modules that are commonly cooled with single-phase convective systems. The long-term reliability of the spray cooling was assessed with 2000 h of testing time. Performance of the presented system proved the spray cooling of power electronics as an attractive option that enables high power densities while maintaining acceptable and uniform device temperatures. In addition, due to the use of high temperature coolant at low flow rates, the spray cooling offers a compact and efficient system design. View full abstract»

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  • Tombstone Initiation Model for Small Form-Factor Surface Mount Passives

    Publication Year: 2012 , Page(s): 1486 - 1491
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    Passive components such as capacitors are shrinking in size in electrical systems in tandem with the device transistor features. With the size shrink comes an increased risk of process-induced defects such as capacitor tombstoning or billboarding. These defects involve poor connectivity of capacitor terminations to the substrates, affecting the electrical performance of the system. We have developed an analytical model to predict the probability of such defects to occur as a function of the design and process factors. The model demonstrates that the surface tension at component terminals dominates over the inertia forces (component weight) in case of components with submilligram weight. Bulkier capacitors have lower risk of tombstoning compared to the lighter ones. The analysis also points to other modulating factors such as component termination width, component height, solder pad size, and the solder paste volume. We also present the experimental results on small form-factor components that confirm some of the predictions for the model. Optimum design guidelines for the electrical systems with soldered components can be obtained from the current model. View full abstract»

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  • Predicting the Effect of Underfill Filler Volume Fraction on Solder Fatigue Life and Residual Stress for Surface Mount Components Using Nonlinear Viscoelastic Analyses

    Publication Year: 2012 , Page(s): 1492 - 1500
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1239 KB) |  | HTML iconHTML  

    Glassy thermoset polymer underfills are commonly used for reliability enhancement in modern electronics. By adding filler to the polymer, underfill mechanical properties, such as bulk and shear moduli and coefficient of thermal expansion, can be altered. Addition of underfills can affect the solder reliability and component failure during dynamic environments. By modifying the nonlinear viscoelastic simplified potential energy clock model, a generic computational tool was created for analyzing filled polymers. Together with a unified creep plasticity model for solder and the Coffin-Manson fatigue criterion, solder fatigue life for underfilled surface mount components was investigated for various underfill filler materials and filler volume fractions (FVFs) using finite element analyses. By creating models of representative components with very different geometries, the effect of adding an underfill and increasing the FVF of hard and glass micro-balloons (GMB) fillers was analyzed. For a large stiff component, the addition of an unfilled underfill reduced the localized tensile stress in the component. Underfill filler volume fractions greater than 10% for hard filler and 15% for GMB filler resulted in a positive effect on the fatigue life. The results were different for a small flexible component. The addition of an unfilled underfill slightly increased the localized tensile stress in the component, but a positive effect on the fatigue life was still demonstrated if the underfill FVFs were greater than 15% for hard filler and 30% for GMB filler. View full abstract»

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  • CMOS RF Transmitter Using Pulsewidth Modulation for Wireless Smart Sensors

    Publication Year: 2012 , Page(s): 1501 - 1509
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    This paper presents the radio frequency (RF) transmitter using pulsewidth modulation (PWM) method. The proposed transmitter can perform with lower power consumption compared to other RF transmitters using a conventional ring oscillator because the proposed voltage-controlled oscillator (VCO) is operated by ON-/OFF-time of the PWM signal. Moreover, the proposed VCO with a metal-oxide semiconductor switch can reduce the power consumption significantly due to the reduction of idle current loss. The power dissipation of the transmitter is measured as 0.75 mW at a carrier of 315 MHz. The transmission of the modulated signal is performed by the on-chip antenna with bond-wire inductor. The on-chip antenna has gain of -34.33 dBi. The radiated power is measured as -32.3 dBm at a distance of 10 cm between the receiver and the transmitter. View full abstract»

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  • Time-Domain Green's Function-Based Parametric Sensitivity Analysis of Multiconductor Transmission Lines

    Publication Year: 2012 , Page(s): 1510 - 1517
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (925 KB) |  | HTML iconHTML  

    We present a new parametric macromodeling technique for lossy and dispersive multiconductor transmission lines. This technique can handle multiple design parameters, such as substrate or geometrical layout features, and provide time-domain sensitivity information for voltages and currents at the ports of the lines. It is derived from the dyadic Green's function of the 1-D wave propagation problem. The rational nature of the Green's function permits the generation of a time-domain macromodel for the computation of transient voltage and current sensitivities with respect to both electrical and physical parameters, completely avoiding similarity transformation, and it is suited to generate state-space models and synthesize equivalent circuits, which can be easily embedded into conventional SPICE-like solvers. Parametric macromodels that provide sensitivity information are well suited for design space exploration, design optimization, and crosstalk analysis. Two numerical examples validate the proposed approach in both frequency and time-domain. View full abstract»

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  • Bended Differential Transmission Line Using Compensation Inductance for Common-Mode Noise Suppression

    Publication Year: 2012 , Page(s): 1518 - 1525
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (817 KB) |  | HTML iconHTML  

    In this paper, a bended differential transmission line using a compensation inductance is proposed to efficiently suppress the common-mode noise. The bended differential transmission line using the compensation inductance can then be implemented by the bended differential transmission line using the short-circuited coupled line. It has been shown that the bended differential transmission line using the short-circuited coupled line can greatly reduce the mode conversion from -5.47 to -14.75 dB, and the time-domain-through common-mode noise from 0.068 to 0.02 V as compared with the bended differential transmission line using the right-angle bend. In order to verify the simulation results, measurement is done in the frequency and time domains where the measurement results are in good agreement with the simulation results. View full abstract»

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  • Substrate-Integrated Waveguide Vertical Interconnects for 3-D Integrated Circuits

    Publication Year: 2012 , Page(s): 1526 - 1535
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1547 KB) |  | HTML iconHTML  

    This paper presents and demonstrates a class of 3-D integration platforms of substrate-integrated waveguide (SIW). The proposed right angle E-plane corner based on SIW technology enables the implementation of various 3-D architectures of planar circuits with the printed circuit board and other similar processes. This design scheme brings up attractive advantages in terms of cost, flexibility, and integration. Two circuit prototypes with both 0- and 45° vertical rotated arms are demonstrated. The straight version of the prototypes shows 0.5 dB of insertion loss from 30 to 40 GHz, while the rotated version gives 0.7 dB over the same frequency range. With this H-to-E-plane interconnect, a T-junction is studied and designed. Simulated results show 20-dB return loss over 19.25% of bandwidth. Measured results suggest an excellent performance within the experimental frequency range of 32-37.4 GHz, with 10-dB return loss and less than ±4° phase imbalance. An optimized wideband magic-T structure is demonstrated and fabricated. Both simulated and measured results show a very promising performance with very good isolation and power equality. With two 45° vertical rotated arm bends, two antennas are used to build up a dual polarization system. An isolation of 20 dB is shown over 32-40 GHz and the radiation patterns of the antenna are also given. View full abstract»

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  • Color Biological Features-Based Solder Paste Defects Detection and Classification on Printed Circuit Boards

    Publication Year: 2012 , Page(s): 1536 - 1544
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1687 KB) |  | HTML iconHTML  

    Deposited solder paste inspection plays a critical role in surface mounting processes. When detecting solder pastes defects on a printed circuit board, profile measurement-based methods suffer from large system size, high cost, and low speed for inspection, although they provide 3-D information of solder pastes. In contrast, image analysis-based methods facilitate the defect detection process of solder pastes by treating them as a pattern recognition problem. However, existing image analysis methods do not perform well because low-level visual features cannot catch sufficient information for defect detection. This paper proposes a new defect detection scheme for solder pastes based on learning the color biological feature sub-manifold. In particular, we apply the biologically inspired color feature (BICF) to represent the solder paste images, and introduce a new sub-manifold learning method to extract the intrinsic low-dimensional BICF manifold embedded in an extrinsic high-dimensional ambient space. This scheme mimics the function of human visual cortex in recognition tasks, and can separate poor quality solder pastes from good quality ones. We apply the new scheme to our automated optical inspection system, and thorough empirical studies indicate the effectiveness of the new scheme for practical utilization. View full abstract»

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  • Height Measurement of Micro-Solder Balls on Metal Pad by White Light Projection

    Publication Year: 2012 , Page(s): 1545 - 1549
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1344 KB) |  | HTML iconHTML  

    Micro-solder balls are commonly used in wafer-level ball grid array (BGA) packages as an interconnection medium. To measure the height of a micro-solder ball on a metal pad, we propose a white light projection method to avoid interference from pads in the shadow of the ball. The optical projection of a solder ball under the illumination of a parallel white light beam is studied, and the relationships between the ball height, ball radius, and shadow length are deduced. An experimental platform with a simple optical system and white light emitting diodes lighting source is constructed to obtain ball and shadow images, and a program developed to process these images and calculate the ball height. The heights of the balls on a BGA chip are measured using this new method, and the results verified using a commercial optical profiler. This method is not sensitive to the patterns on the substrate surface and has great potential for future application. View full abstract»

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  • Effect of Capillary Trace on Dynamic Loop Profile Evolution in Thermosonic Wire Bonding

    Publication Year: 2012 , Page(s): 1550 - 1557
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2026 KB) |  | HTML iconHTML  

    Thermosonic wire bonding remains the most commonly used interconnection technology in microelectronic packaging, and looping is an important aspect in modern wire bonders. To identify the loop formation mechanism, the effect of capillary trace on the standard wire looping process was studied. Dynamic looping processes with different capillary trace parameters and reverse motions of 4, 8, and 16 mil were recorded by a high-speed camera. The capillary trace and wire profile evolution were obtained from the looping videos using a digital image processing program, and the relationship between capillary trace and loop profiles was analyzed. A finite-element model was established to study the strain distribution on wire during looping. Experimental and simulation results show that the wire profile of the standard loop is mainly affected by capillary position and is not sensitive to capillary velocity. The upward capillary trace mainly affects the loop configuration, including the number, position, and deformation of kinks and the loop length. The downward capillary trace affects the stress states, loop height, kink deformation, and loop profiles. A kink is the wire with the largest local curvature, and it is a plastically deformed wire segment with little elastic core. The kink has two functions: 1) shaping the loop and 2) isolating the pulling force on the first bond and neck caused by capillary movement. This paper can be of great help in loop profile optimization in the industry and in academic research of loop dynamics. View full abstract»

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  • Analysis of the Electronic Assembly Repair Process for Lead-Free Parts Under Combined Loading Conditions

    Publication Year: 2012 , Page(s): 1558 - 1567
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1427 KB) |  | HTML iconHTML  

    The conversion from tin-lead (SnPb) to lead-free electronics has created concern amongst engineers about the reliability of electronic assemblies and the ramifications that reliability changes may have on the life-cycle cost and availability of critical systems that use lead-free electronics. In this paper, the impact of lead-free solder on the repair of electronic assemblies subject to combined thermal and vibration loading is studied. The cost, repair time, and availability of boards are quantified using a previously developed repair simulator for a test board developed and tested by the Joint Council on Aging Aircraft & Joint Council on Pollution Prevention that includes ceramic leadless chip carrier, thin small outline package, and plastic ball grid array packaged parts using SnPb and lead-free solders. This paper describes the process of calibrating a physics-of-failure reliability simulator using experimental highly accelerated life testing test results for a specific board assembly and using the calibrated model to generate failure distributions corresponding to combined thermal and vibration loading over an actual product life cycle for use in the repair simulator. The results of the repair simulation indicate that longer dwell times appear to cause more damage than larger ΔT; under combined loading conditions, SnPb appears to be more reliable than tin-silver-copper (for the board and parts considered in this paper) and as a result, repair cost is lower; and the number of failures and repair times track repair costs (depending on the capacity of repair process). View full abstract»

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    Publication Year: 2012 , Page(s): 1568
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    Publication Year: 2012 , Page(s): 1569
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Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University