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Device and Materials Reliability, IEEE Transactions on

Issue 3 • Date Sept. 2012

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Displaying Results 1 - 13 of 13
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Device and Materials Reliability publication information

    Page(s): C2
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  • Changes to the Editorial Board of T-DMR

    Page(s): 537
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  • Influence of Large-Aspect-Ratio Surface Roughness on Electrical Characteristics of AlGaN/AlN/GaN HFETs

    Page(s): 538 - 546
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1037 KB) |  | HTML iconHTML  

    The effect of large-aspect-ratio surface roughness of AlGaN/GaN wafers is investigated. The roughness has a surface morphology consisting of hexagonal peaks with maximum peak-to-valley height of more than 100 nm and lateral peak-to-peak distance between 25 and 100 μm. Two epitaxial wafers grown at the same time on SiC substrates having different surface orientation and with a resulting difference in AlGaN surface roughness are investigated. Almost no difference is seen in the electrical characteristics of the materials, and the electrical uniformity of the rough material is comparable to that of the smoother material. The reliability of heterostructure field-effect transistors from both materials have been tested by stressing devices for up to 100 h without any significant degradation. No critical effect, from the surface roughness, on device fabrication is experienced, with the exception that the roughness will directly interfere with step-height measurements. View full abstract»

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  • Investigation of the High-Temperature Operation of AlGaN/GaN HFETs via Studying the Impact of Temperature Dependency of Drift Transport Characteristics

    Page(s): 547 - 553
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    Investigation of the reliable operation of AlGaN/GaN HFETs at elevated temperatures is attempted. In this paper, a Monte Carlo-based temperature-dependent mobility model, with incorporation of steady-state velocity overshoot, is employed in modeling the drain current-voltage characteristics of AlGaN/GaN HFETs at 300, 400, and 500 K. One of the major merits of this model is that it employs a very small set of fitting parameters. The modeled drain current-voltage characteristics have been successfully matched to the experimental characteristics at the aforementioned temperatures. While confirming that a brief measurement at these temperatures is of no reliability concern on the quality of the metal-semiconductor contacts, this matching proves that the temperature dependency of the electron drift velocity is the cause of the degradation of drain current within the aforementioned range of temperature. In producing the aforementioned match for the long-gate AlGaN/GaN HFETs, it is also shown that the accurate modeling of the temperature dependency of the low-field drift transport is more consequential than the accurate representation of the transport in the medium-to-high electric fields. View full abstract»

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  • Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology

    Page(s): 554 - 561
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (841 KB) |  | HTML iconHTML  

    Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection. View full abstract»

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  • Effect of Elevated Ambient Temperature on Thermal Breakdown Behavior in BCD ESD Protection Devices Subjected to Long Electrical Overstress Pulses

    Page(s): 562 - 569
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (902 KB) |  | HTML iconHTML  

    We investigate the effect of elevated ambient temperature on thermal breakdown (TB) modes in linear-geometry electrostatic discharge (ESD) protection n-p-n transistors of smart power technology subjected to 0.5-1- μs-long ESD pulses. The current transport in these devices has a form of traveling current filaments (CFs) where TB at room temperature occurs at one of the device ends. An increase in ambient temperature gives rise additionally to another failure mode, inside the device. For the failure mode at the device end, the increase of ambient temperature in the range up to 100°C causes shortening of the averaged time to TB 〈tTB〉 by a duration that the CF needs for one round trip over the device width. At ambient temperatures up to 180°C, the TB may occur even at initial triggering CF position inside the device, before the CF starts to move. The ambient temperature at which the transition between CF modes with different 〈tTB〉 occurs is investigated as a function of stress current. Furthermore, inspecting the failure current of devices with different widths shows that there is an equivalence between the effect of increased ambient temperature and the effect of the preheating at the device end by a previous CF passage. The experiments are supported by 3-D thermal simulation of temperature in moving and standing CFs. View full abstract»

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  • Magnetic Instability in Tunneling Magnetoresistive Heads Due to Temperature Increase During Electrostatic Discharge

    Page(s): 570 - 575
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    Recently, there has been a growing interest in the effects of electrostatic discharge (ESD) failure on tunneling magnetoresistive (TMR) recording heads because it directly affects reliability in manufacturing of these heads. Therefore, we study the magnetic degradation in TMR junctions caused by the temperature increase using three different ESD models. A 3-D finite-element method is used for analyzing the spatial and temporal profiles of the temperature during the discharge. The results from the three models show that, although the highest temperature occurs in the MgO barrier layer, the initial magnetic modification likely arises in the IrMn antiferromagnetic layer due to its low Néel temperature. We also found that the increase in temperature is proportional to the square of the ESD voltage. The magnetic instability of the antiferromagnetic layer due to the ESD effect is the important parameter realized for development of the future TMR devices. View full abstract»

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  • A Simulation Study of Colpitts Oscillator Reliability and Variability

    Page(s): 576 - 581
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    Nanoscale CMOS reliability and process variation effect on the LC Colpitts oscillator has been examined. Mixed-mode device and circuit simulation is used to investigate the physical insight of impact ionization to the Colpitts oscillator. An analytical equation of phase noise as a function of offset frequency, transistor parameters, and body bias has been derived. The analytical predictions are in good agreement with ADS simulation results. An adaptive body bias to minimize process variation effect on the Colpitts oscillator has also been proposed. The adaptive body bias technique effectively reduces the hot electron effect and process variability on the Colpitts oscillator performance, as supported by Monte Carlo simulation results. View full abstract»

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  • Corrections to “Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias” [Jun 12 225-232]

    Page(s): 582
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    In the above titled paper (ibid., vol. 12, no. 2, pp. 225-232, June 2012), Fig. 1 did not appear correctly. The corrected Fig. 1 is presented here. View full abstract»

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  • Special Issue on GaN Electronic Devices

    Page(s): 583 - 584
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  • IEEE Transactions on Device and Materials Reliability information for authors

    Page(s): C3
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  • [Blank page - back cover]

    Page(s): C4
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Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.