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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Publication Year: 2012, Page(s): C1
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• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2012, Page(s): C2
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• FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture

Publication Year: 2012, Page(s):1305 - 1318
Cited by:  Papers (1)
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Guarded evaluation is a power reduction technique that involves identifying subcircuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not “observable&#x... View full abstract»

• Automatic Decoder Synthesis: Methods and Case Studies

Publication Year: 2012, Page(s):1319 - 1331
Cited by:  Papers (1)
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Upon receiving the output sequence streaming from a sequential encoder, a decoder reconstructs the corresponding input sequence that streamed to the encoder. Such an encoding and decoding scheme is commonly encountered in communication, cryptography, signal processing, and other applications. Given an encoder specification, decoder design can be error-prone and time consuming. Its automation may h... View full abstract»

• Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits

Publication Year: 2012, Page(s):1332 - 1345
Cited by:  Papers (2)
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Stability analysis is one of the key challenges in analog circuit design. As feature sizes continue to shrink and the effect of parasitics becomes more dominant, we are forced to deal with stability analysis of increasingly complex multiloop structures with potentially hundreds of loops-a task that can no longer be dealt with using traditional methods. An automated stability checker tool that dete... View full abstract»

• MTFS: Mixed Time–Frequency Method for the Steady-State Analysis of Almost-Periodic Nonlinear Circuits

Publication Year: 2012, Page(s):1346 - 1355
Cited by:  Papers (1)
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Periodic circuits driven by multitone signals are still a challenging simulation problem despite several numerical methods being presented in the literature. In this paper, a mixed time-frequency method for the solution of this problem and suitable for both autonomous and nonautonomous circuits is presented. The method is based on an extension of the envelope following method, which allows us to r... View full abstract»

• NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing

Publication Year: 2012, Page(s):1356 - 1365
Cited by:  Papers (2)
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In this paper, we introduce and study the rectangle escape problem (REP), which is motivated by printed circuit board (PCB) bus escape routing. Given a rectangular region R and a set S of rectangles within R, the REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove th... View full abstract»

• Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs

Publication Year: 2012, Page(s):1366 - 1378
Cited by:  Papers (7)
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A modern chip often contains large numbers of predesigned macros (e.g., embedded memories, IP blocks) and standard cells, with very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has caused significant challenges to modern circuit placement. Analytical algorithms have been shown to be most effective for standard-cell placement, but the pro... View full abstract»

• DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Publication Year: 2012, Page(s):1379 - 1392
Cited by:  Papers (9)
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Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout character... View full abstract»

• Fast Timing-Model Independent Buffered Clock-Tree Synthesis

Publication Year: 2012, Page(s):1393 - 1404
Cited by:  Papers (3)
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In high-performance synchronous chip design, a buffered clock tree with small clock skew is essential for improving clocking speed. Due to the insufficient accuracy of timing models for modern chip design, embedding simulation into a clock-tree synthesis flow becomes inevitable. Consequently, the running time for clock-tree synthesis becomes prohibitively huge as the complexity of chip designs gro... View full abstract»

Publication Year: 2012, Page(s):1405 - 1416
Cited by:  Papers (8)
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This paper describes a method for improving the test quality of digital circuits on a per-design basis by: 1) monitoring the defect behaviors that occur through volume diagnosis; and 2) changing the test patterns to match the identified behaviors. To characterize the behavior of a defect (i.e., the conditions when a defect is activated), physically-aware diagnosis is employed to extract the set of... View full abstract»

• $X$-Canceling MISR Architectures for Output Response Compaction With Unknown Values

Publication Year: 2012, Page(s):1417 - 1427
Cited by:  Papers (9)
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In this paper, an X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output responses containing unknown X values is described. Each bit of the MISR signature is expressed as a linear combination in terms of Xs by symbolic simulation. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed t... View full abstract»

• Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage

Publication Year: 2012, Page(s):1428 - 1438
Cited by:  Papers (3)
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Test generation procedures for n -detection test sets improve the quality of a test set by adding tests that increase the numbers of detections of target faults. A different approach to n-detection test generation increases the numbers of detections of target faults within the bounds of the number of tests of a single-detection test set. Multicycle tests provide the flexibility of im... View full abstract»

• Verifying Coalitions in 3-Party Systems

Publication Year: 2012, Page(s):1439 - 1451
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Multiplayer games are played by a set of agents, where, at each round, all players give their moves, and the combination of their moves defines the successor states for the game. In such games, the players pursue certain goals with their moves and in that pursuit, they can form coalitions to fulfill a common objective. In this paper, we adopt this model of multiplayer coalition games in the contex... View full abstract»

• Estimation of dc Performance of a Lateral Power MOSFET Using Distributed Cell Model

Publication Year: 2012, Page(s):1452 - 1456
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This paper presents a technique to study and estimate the dc performance of lateral power MOSFET switches used in on-chip dc-dc converters. The dc performance is characterized by the on-resistance and current distribution profile in the switch layout. In the proposed approach, a netlist is generated that consists of the parasitic resistances extracted from the metal interconnects along with the MO... View full abstract»

• Analog IC Variability Bound Estimation Using the Cornish–Fisher Expansion

Publication Year: 2012, Page(s):1457 - 1461
Cited by:  Papers (2)
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In nanoscale integrated circuit technologies, process parameter fluctuations gain increasingly in importance. Efficient methods are thus required during the design phase to evaluate the resulting variability. In this letter, we propose a new method to estimate the variation bounds of analog circuit performance. This method combines design of experiment techniques with the Cornish-Fisher expansion:... View full abstract»

Publication Year: 2012, Page(s): 1462
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• 2012 IEEE membership form

Publication Year: 2012, Page(s):1463 - 1464
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• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2012, Page(s): C3
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• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

Publication Year: 2012, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu