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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 8 • Date Aug. 2012

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2012 , Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2012 , Page(s): C2
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  • Low-Power SiGe BiCMOS Transimpedance Amplifier for 25-GBaud Optical Links

    Publication Year: 2012 , Page(s): 461 - 465
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    We propose a new circuit for the realization of transimpedance amplifiers (TIAs), targeted at reducing the input-referred noise of the TIA or alternatively increasing the bandwidth, without increasing the power dissipation. An intensive theoretical analysis of the method is given. A prototype chip is fabricated in 0.25- \mu\hbox {m} SiGe BiCMOS technology. The TIA has a gain of 71 \hbox {dB}\Omega , a bandwidth of 20.5 GHz, and an average input-referred current noise density of 18 \hbox {pA}/\surd \hbox {Hz} . The circuit operates from a 2.5-V supply, and power dissipation is 57 mW. View full abstract»

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  • A Phasor-Domain Study of Lock Range of Harmonic Oscillators With Multiple Injections

    Publication Year: 2012 , Page(s): 466 - 470
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    This brief presents a phasor-domain study of the lock range of harmonic oscillators with multiple injections. The intrinsic relation between the lock range of harmonic oscillators with multiple injections and that with a single injection is obtained. We show that harmonic oscillators with multiple injections exhibit a larger lock range as compared with those with single injection if the phase of the injection signals is properly chosen. We further show that the maximum lock range provided by dual injections is twice that provided by a single injection. The findings are verified using LC oscillators with a single injection and dual injections designed in IBM 130-nm 1.2-V CMOS technology. View full abstract»

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  • Hardware-Accelerated Simulation Environment for CT Sigma–Delta Modulators Using an FPGA

    Publication Year: 2012 , Page(s): 471 - 475
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    In this brief, a hardware-accelerated simulation environment for continuous-time (CT) \Sigma \Delta modulators is presented. Due to the presence of the nonlinear quantizer, simulating \Sigma \Delta modulators is a complicated task in general. The simulation of CT modulators is even more time consuming than that of their discrete-time counterparts, due to the analog loop filter. In particular, in an automated design environment, a large number of simulations have to be performed during the design process of  \Sigma \Delta modulators. In this brief, it is shown for the first time that the system-level emulation of CT \Sigma \Delta modulators on an field-programmable gate array results in a significant acceleration, reducing the simulation time by a factor of more than \hbox {10}^{5} compared to a commonly used Simulink simulation. This allows simulating 10 000 of modulators per second, enabling the use of heuristic search algorithms for real-time design for CT \Sigma \Delta modulators. View full abstract»

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  • Internally Non-LTI Systems Based on Delays, With Application to Companding Signal Processors

    Publication Year: 2012 , Page(s): 476 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (150 KB) |  | HTML iconHTML  

    We convert linear continuous-time systems based on delays to internally nonlinear ones, with unchanged input–output behavior. The internal nonlinearities can be chosen so that the internal modified noise transfer functions result in improved output signal-to-noise ratio for small inputs, thus extending the usable dynamic range. This results in companding signal processors, of which two examples are given—one using syllabic and one using instantaneous companding. This study complements earlier work on externally linear continuous-time systems with rational transfer functions and on such systems containing discrete-time delays. View full abstract»

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  • An Adaptive Reconfigurable Active Voltage Doubler/Rectifier for Extended-Range Inductive Power Transmission

    Publication Year: 2012 , Page(s): 481 - 485
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1029 KB) |  | HTML iconHTML  

    We present an adaptive reconfigurable active voltage doubler (VD)/rectifier (REC) (VD/REC) in standard CMOS, which can adaptively change its topology to either a VD or a REC by sensing the output voltage, leading to more robust inductive power transmission over an extended range. Both active VD and REC modes provide much lower dropout voltage and far better power conversion efficiency (PCE) compared to their passive counterparts by adopting offset-controlled high-speed comparators that drive the rectifying switches at proper times in the high-frequency band. We have fabricated the active VD/REC in a 0.5- \mu\hbox {m} 3-metal 2-poly CMOS process, occupying 0.585 \hbox {mm}^{2} of chip area. In an exemplar setup, VD/REC extended the power transmission range by 33 % (from 6 to 8 cm) in relative coil distance and 41.5 % (from 53 ^{\circ} to 75 ^{\circ} ) in relative coil orientation compared to using the REC alone. While providing 3.1-V dc output across a 500- \Omega load from 2.15- (VD) and 3.7-V (REC) peak ac inputs at 13.56 MHz, VD/REC achieved measured PCEs of 70 % and 77 % , respectively. View full abstract»

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  • A Compact Rail-to-Rail Class-AB CMOS Buffer With Slew-Rate Enhancement

    Publication Year: 2012 , Page(s): 486 - 490
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (589 KB) |  | HTML iconHTML  

    Two prior-art transconductance amplifier-based rail-to-rail class-AB analog buffers are examined. Their analysis reveals that the output current drive capability for large input voltages is restricted. To mitigate this drawback, a relatively simple slew-rate enhancement scheme is proposed. The new scheme allows the buffer's speed to be increased by over 200% with only a very small increase in static power consumption (1.25%) and silicon area (3%). The proposed and the two conventional buffers were fabricated in a 0.35- \mu \hbox {m} CMOS technology for a power supply of 3 V. Measurements verify the superior slew-rate performance of the new buffer for rail-to-rail step responses. View full abstract»

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  • A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS

    Publication Year: 2012 , Page(s): 491 - 495
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    Low-power (LP) high-speed serial I/O transmitters which include equalization to compensate for channel frequency-dependent loss are required to meet the aggressive link energy-efficiency targets of future systems. This brief presents an LP serial-link-transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in predriver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic-power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Fabricated in a 1.2-V 90-nm LP CMOS process, the transmitter supports an output swing range of 100–400 \hbox {mV}_{{\rm ppd}} and up to 6 dB of equalization and includes output-duty-cycle control. The transmitter achieves 6-Gbit/s operation at 1.26-pJ/bit energy efficiency with 300- \hbox {mV}_{{\rm ppd}} output swing and 3.72-dB equalization. View full abstract»

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  • Efficient Digital Implementation of Extreme Learning Machines for Classification

    Publication Year: 2012 , Page(s): 496 - 500
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    The availability of compact fast circuitry for the support of artificial neural systems is a long-standing and critical requirement for many important applications. This brief addresses the implementation of the powerful extreme learning machine (ELM) model on reconfigurable digital hardware (HW). The design strategy first provides a training procedure for ELMs, which effectively trades off prediction accuracy and network complexity. This, in turn, facilitates the optimization of HW resources. Finally, this brief describes and analyzes two implementation approaches: one involving field-programmable gate array devices and one embedding low-cost low-performance devices such as complex programmable logic devices. Experimental results show that, in both cases, the design approach yields efficient digital architectures with satisfactory performances and limited costs. View full abstract»

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  • Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

    Publication Year: 2012 , Page(s): 501 - 505
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    In this brief, we present a hardware-based Gaussian noise generator (GNG) with low hardware cost, high generation rate, and high Gaussian tail accuracy. The proposed generator is based on a piecewise polynomial approximation of the inverse cumulative distribution function (ICDF). We propose to avoid the area-demanding barrel-shifter of the ICDF approximation by means of creating a new uniform random sequence from the uniform random number generator output. The GNG architecture has been implemented in field-programmable gate array devices, and the implementation results are compared with other published designs, achieving a higher deviation with fewer hardware resources. Our GNG generates 242 Msps of random noise and achieves a tail of 13.1 \sigma with 442 slices, two multipliers, and two Block-RAM of a Virtex-II device. The generator output successfully passed commonly used statistical tests. View full abstract»

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  • FPGA Design for Statistics-Inspired Approximate Sum-of-Squared-Error Computation in Multimedia Applications

    Publication Year: 2012 , Page(s): 506 - 510
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    This brief introduces a low-cost hardware design for approximate squaring functions which preserve maximum information content of the signals in template-matching applications. Analysis of signal statistics for two example applications, i.e., motion estimation and disparity estimation, is presented. This information is then specifically incorporated in the hardware design process to develop approximate squarers which outperform existing designs in hardware resource savings and performance while processing real-world data. Specifically, the proposed architectures make distinction between low- and high-entropy portions of the input data to intelligently trade off bit precision with hardware complexity. Mathematical and experimental results show mean-relative-error figures to be as low as 1.2% and the performance to be as good as conventional full-precision processing scenarios. Implementation results for current-generation six-input look up table (LUT) and four-input LUT FPGAs have been discussed in relation to the proposed design flow. View full abstract»

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  • Corrections to ‘Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping’

    Publication Year: 2012 , Page(s): 511 - 514
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (465 KB) |  | HTML iconHTML  

    Islam and Wahid proposed an area- and power-efficient design of Daubechies wavelet transforms. However, it was found that the matrix decompositions of the folded algebraic-integer-quantization scheme for DAUB4 and DAUB6 are incorrect and do not correspond with their architecture designs. We propose modifications not only to the algorithm but also to its implementation. Compared with the original method, the proposed design requires fewer adders and maintains the same critical path. View full abstract»

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  • On Sampled-Data Control for Master-Slave Synchronization of Chaotic Lur'e Systems

    Publication Year: 2012 , Page(s): 515 - 519
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (142 KB) |  | HTML iconHTML  

    This brief presents a new method for master-slave synchronization of chaotic Lur'e systems with sampled-data control. The new method is based on a novel construction of piecewise differentiable Lyapunov functionals in the framework of the input delay approach. The new Lyapunov functional is continuous at sampling times but not necessarily positive definite inside the sampling intervals. Compared with the existing works, the proposed method makes full use of the information on the piecewise constant input and the actual sampling pattern. Two illustrative examples are given which substantiate the usefulness of the proposed method. View full abstract»

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  • Stabilization of Bilinear Power Converters by Affine State Feedback Under Input and State Constraints

    Publication Year: 2012 , Page(s): 520 - 524
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    This brief presents a novel systematic procedure for the synthesis of affine state-feedback control laws for power converters. The proposed synthesis method is applicable to power converters with a bilinear averaged model and comes with a guarantee of closed-loop stability under hard state and input constraints. The low complexity of the resulting control law translates into a reduced cost of the control hardware, while nonconservative constraint handling yields a higher reliability of the power converter. Moreover, the incorporation of state constraints in controller synthesis can be exploited to achieve a higher power density for the converter. The effectiveness of the proposed controller synthesis method is illustrated on a buck-boost converter case study. Both simulation and real-time experimental results are reported. View full abstract»

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  • DOB Design for Nonminimum-Phase Delay Systems and Its Application in Multivariable MPC Control

    Publication Year: 2012 , Page(s): 525 - 529
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    This brief first presents an improved disturbance observer (IDOB) design method to deal with disturbance observation for the nonminimum-phase delay systems. Then, an IDOB-based compound control scheme is developed to enhance the disturbance rejection performance of multivariable model predictive control (MPC) under various disturbances and uncertainties. In such an IDOB–MPC scheme, the MPC controller acts as a prefilter and generates appropriate control actions such that a desired setpoint tracking response is achieved. The IDOB is used to estimate the various disturbances dynamically and suppress them by feedforward compensation design. Both theory analysis and simulation comparisons have shown good disturbance estimation and rejection performances of the proposed method. View full abstract»

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  • ISCAS 2013

    Publication Year: 2012 , Page(s): 530
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  • Special issue on ultra low voltage vlsicircuits and systems

    Publication Year: 2012 , Page(s): 531
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

    Publication Year: 2012 , Page(s): 532
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2012 , Page(s): C3
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  • [Blank page - back cover]

    Publication Year: 2012 , Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope