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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 12 • Date Dec. 2012

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Displaying Results 1 - 25 of 25
  • Table of Contents

    Page(s): C1 - C4
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Page(s): C2
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  • Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume

    Page(s): 2157 - 2169
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1133 KB) |  | HTML iconHTML  

    We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead. View full abstract»

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  • Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

    Page(s): 2170 - 2183
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    XOR network-based on-chip test compression schemes have been widely employed in large industrial scan designs due to their high compression ratio and efficient decompression mechanism. Nevertheless, such a scheme necessitates high unspecified bit ratios in the original test cubes, resulting in quite significant difficulties in preprocessing test cubes for scan power reduction. The linear mapping from the original cubes to the compressed seeds typically provides extra degrees of flexibility as multiple seeds may reconstruct the test cube. Due to the highly divergent power impact of distinct seeds though, appreciable power reductions in the decompressed test data can be attained through the pinpointing of the power-optimal seeds during the compression phase. This work explores the aforementioned flexibility in the seed space, and outlines a mathematical and algorithmic framework for a power-aware linear test compression scheme. The proposed technique incurs no hardware overhead over the traditional linear compression scheme; it can be easily embedded furthermore into the industrial test compaction/compression flow. Experimental results confirm that the proposed technique delivers significant scan power reduction with negligible impact on the compression ratio. View full abstract»

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  • Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow

    Page(s): 2184 - 2197
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    A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic gate. We devise four new VCLBs and construct several cell libraries based on these VCLBs. We develop a design flow mostly using industrial design tools and propose a method to evaluate VCLB viability. The experimental results show that a medium-grained VCLB that realizes a rich set of logic functions attains the best performance. View full abstract»

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  • An FPGA Chip Identification Generator Using Configurable Ring Oscillators

    Page(s): 2198 - 2207
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    Physically unclonable functions (PUF) are commonly used in applications such as hardware security and intellectual property protection. Various PUF implementation techniques have been proposed to translate chip-specific variations into a unique binary string. It is difficult to maintain repeatability of chip ID generation, especially over a wide range of operating conditions. To address this problem, we propose utilizing configurable ring oscillators and an orthogonal re-initialization scheme to improve repeatability. An implementation on a Xilinx Spartan-3e field-programmable gate array was tested on nine different chips. Experimental results show that the bit flip rate is reduced from 1.5% to approximately 0 at a fixed supply voltage and room temperature. Over a 20 °C-80 °C temperature range and 25% variation in supply voltage, the bit flip rate is reduced from 1.56% to 3.125×10-7. View full abstract»

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  • Real-Time Architecture for a Robust Multi-Scale Stereo Engine on FPGA

    Page(s): 2208 - 2219
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    In this work, we present a real-time implementation of a stereo algorithm on field-programmable gate array (FPGA). The approach is a phase-based model that allows computation with sub-pixel accuracy. The algorithm uses a robust multi-scale and multi-orientation method that optimizes the estimation extraction with respect to the local image structure support. With respect to the state of the art, our work increases the on-chip power of computation compared to previous approaches in order to obtain a good accuracy of results with a large disparity range. In addition, our approach is specially suited for unconstrained environments applications thanks to the robustness of the phase information, capable of dealing with severe illumination changes and with small affine deformation between the image pair. This work also includes the rectification images circuitry in order to exploit the epipolar constraints on the chip. The dedicated circuit can rectify and process images of VGA resolution at a frame rate of 57 fps. The implementation uses a fine pipelined method (also with superscalar units) and multiple user defined parameters that lead to a high working frequency and a good adaptability to different scenarios. In the paper, we present different results and we compare them with state of the art approaches. View full abstract»

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  • Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits

    Page(s): 2220 - 2231
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    Design of analog integrated circuits is discussed in this paper. The emphasis is on the biasing design of ICs using Fixator-norator pairs. Fixators are used to keep the driver transistors biased at the desirable operating points while the pairing norators are used to allocate and specify the bias-supporting components. A bias-supporting component is shown to be one of the two categories: 1) a DC voltage source or a DC current source/sink or 2) a power-conducting component. A power-conducting component is typically a resistor in lumped circuits but an active load or current mirror in an analog IC. Three types of active loads are introduced and their design is also discussed in this paper. Two examples, one in bipolar and one in CMOS technology, demonstrate the analog IC design procedure. View full abstract»

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  • A 64 \times 64 Pixels UWB Wireless Temporal-Difference Digital Image Sensor

    Page(s): 2232 - 2240
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    In this paper we present a low power temporal-difference image sensor with wireless communication capability designed specifically for imaging sensor networks. The event-based image sensor features a 64 × 64 pixel array and can also report standard analog intensity images. An ultra-wide-band radio channel allows to transmit digital temporal difference images wirelessly to a receiver with high rates and reduced power consumption. The sensor can wake up the radio when it detects a specific number of pixels intensity modulation, so that only significant frames are communicated. The prototype chip was implemented using a 2-poly 3-metal AMIS 0.5 μ m CMOS process. Power consumption is 0.9 mW for the sensor and 15 mW for radio transmission to distance of 4 m with rates of 1.3 Mbps and 160 fps. View full abstract»

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  • Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications

    Page(s): 2241 - 2254
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    A broadband digital beamforming algorithm is proposed for directional filtering of temporally-broadband bandpass space-time plane-waves at radio frequencies (RFs). The enhancement of desired waves, as well as rejection of undesired interfering plane-waves, is simulated. A systolic- and wavefront-array architecture is proposed for the real-time implementation of second-order spatially-bandpass (SBP) 2-D infinite impulse response (IIR) beam filters having potential applications in broadband beamforming of temporally down-converted RF signals. The higher speed of operation and potentially reduced power consumption of the asynchronous architecture of wavefront-array processors (WAPs) in comparison to the conventional synchronous hardware has emerging applications in radio-astronomy, radar, navigation, space science, cognitive radio, and wireless communications. Further, the bit error rate (BER) performance improvement along with the reduced computational complexity of the 2-D IIR SBP frequency-planar digital filter over digital phased array feed (PAF) beamformer is provided. A nominal BER versus signal-to-interference ratio (SIR) gain of 10-16 dB compared to case where beamforming is not applied, and a gain of 2-3 dB at approximately half the number of parallel multipliers to digital PAF, are observed. The results of application-specific integrated circuit (ASIC) synthesis of the digital filter designs are also presented. View full abstract»

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  • A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction

    Page(s): 2255 - 2264
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    To guarantee that an application-specific integrated circuit (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suffers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. However, the effectiveness of X-filling depends on the number and the characteristic of X-bit distribution. In this paper, we propose a physical-location-aware X-identification which redistributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X-filling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which redistributes X-bits evenly in all test vectors. View full abstract»

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  • Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput

    Page(s): 2265 - 2277
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    A high-throughput and low-energy semi-serial on-chip communication link based on novel design techniques and circuit solutions is presented. This self-timed link is designed using high-speed serialization/deserializtion and pulse dual-rail encoding techniques. The link also employs wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit-serial links in parallel, mainly comes from the sharing of the novel serializer's control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to the power reduction. Furthermore, the formulated pulse dual-rail encoding provides an opportunity to implement pulse signaling at no cost. The ability to detect data validity at bit level allows acknowledgment per word without losing the delay-insensitivity of the transmission. The proposed semi-serial link is analyzed and compared with bit-serial and fully bit-parallel links for 64-bit data and communication distances of 1 to 8 mm. The semi-serial link which consists of eight bit-serial links provides 72.72 Gbps throughput with 286 fJ/bit energy dissipation for 8 mm transmission. It dissipates the lowest energy per bit compared to fully bit-parallel links while achieving the same throughput. The links are designed and simulated in Cadence Analog Spectre using 65-nm technology from STMicroelectronics. View full abstract»

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  • Efficient Memory Repair Using Cache-Based Redundancy

    Page(s): 2278 - 2288
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    In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a set of direct-mapped cache banks to replace faulty words. Statistical and mathematical probability analysis shows that the proposed scheme achieves high repairability levels with low area and static power dissipation overheads, the latter being a dominant issue in nanometer technologies. It is therefore a suitable solution along with other mature memory repair techniques, to enhance the overall repairability features and guarantee the correct and reliable operation of embedded memories in nanometer technologies. View full abstract»

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  • System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands

    Page(s): 2289 - 2301
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    Adaptive body biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of “body-bias islands,” each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation technique to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed methodology; we demonstrate up to 40% and 60% reduction in the mean and standard deviation of leakage power dissipation respectively, compared to a baseline system without ABB. Furthermore, the proposed design-time partitioning is, on average, 38× faster than a previously proposed Monte Carlo-based technique, while providing similar reductions in leakage power dissipation. View full abstract»

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  • Product Code Schemes for Error Correction in MLC NAND Flash Memories

    Page(s): 2302 - 2314
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    Error control coding (ECC) is essential for correcting soft errors in Flash memories. In this paper we propose use of product code based schemes to support higher error correction capability. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns and have reduced hardware overhead. Simulation results show that product codes can achieve better performance compared to both Bose-Chaudhuri-Hocquenghem codes and plain RS codes with less area and low latency. We also propose a flexible product code based ECC scheme that migrates to a stronger ECC scheme when the numbers of errors due to increased program/erase cycles increases. While these schemes have slightly larger latency and require additional parity bit storage, they provide an easy mechanism to increase the lifetime of the Flash memory devices. View full abstract»

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  • A Hierarchical Self-Repairing Architecture for Fast Fault Recovery of Digital Systems Inspired From Paralogous Gene Regulatory Circuits

    Page(s): 2315 - 2328
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    Self-repairing digital systems have received increasing attention as modern systems are getting more complex and fast. Currently available self-repairing architectures have, however, some limitations such as storage overhead required to prepare all possible rewiring strategies and temporal incorrectness caused by elongated repairing time. In this paper, we propose a novel self-repairing architecture for fast fault recovery with an efficient use of limited resources, which can be easily applied to real complex digital systems. The proposed architecture consists of three layers: a working layer, a control layer, and an interface layer. The working layer employs a hybrid scheme of using both redundant and empty cells with a newly devised self-test. This relieves the overhead of redundant cells required to be prepared in advance by considering every possible fault situation. In the control layer, an ordered assignment control is proposed. The order of working-priority of each processor that controls a normal cell in the working layer is predetermined. A faulty processor is detected by a majority decision among neighboring control processors and corrected by rearranging the order of working-priority. The interface layer connects an external PC for reprogramming. Through this fault recovery mechanism, the system can keep normal functioning under noisy environments. We implemented the proposed self-repairing architecture using an field-programmable gate array board with an application of a dot-matrix LED display and verified its robust operation. The proposed architecture can be widely used as a new platform for self-repairing systems. View full abstract»

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  • Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution

    Page(s): 2329 - 2332
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    Feature matching is an indispensable process for object recognition, which is an important issue for wearable devices with video analysis functionalities. To implement a low-power SoC for object recognition, the proposed visual vocabulary processor (VVP) is employed to accelerate the speed of feature matching. The VVP can transform hundreds of 128-D SIFT vectors into a 64-D histogram for object matching by using the binary-tree-based architecture, and 16 calculators for the computations of the Euclidean distances are designed for each of the two processors in each level. A total of 126 visual words can be saved in the six-level hierarchical memory, which instantly offers the data required for the matching process, and more than 5 times of bandwidth can be saved compared with the non-binary-tree-based architecture. As a part of the recognition SoC, the VVP is implemented with the 65-nm CMOS technology, and the experimental results show that the gate count and the average power consumption are 280 K and 5.6 mW, respectively. View full abstract»

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  • Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

    Page(s): 2333 - 2337
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    The increasing power consumption of processors has made power reduction a first-order priority in processor design. Voltage scaling is one of the most powerful power-reduction techniques introduced to date, but is limited to some minimum voltage VDDMIN. Below VDDMIN on-chip SRAM cells cannot all operate reliably due to increased process variability with technology scaling. The use of larger SRAM cells, which are less sensitive to process variability, allows a reduction in VDDMIN. However, since the large-scale memory structures such as last-level caches (LLCs) often determine the VDDMIN of processors, these structures cannot afford to use large SRAM cells due to the resulting increase in die area. In this paper we first propose a joint optimization of LLC cell size, the number of redundant cells, and the strength of error-correction coding (ECC) to minimize total SRAM area while meeting yield and VDDMIN targets. The joint use of redundant cells and ECC enables the use of smaller cell sizes while maintaining design targets. Smaller cell sizes more than make up for the extra cells required by redundancy and ECC. In 32-nm technology our joint approach yields a 27% reduction in total SRAM area (including the extra cells) when targeting 90% yield and 600 mV VDDMIN. Second, we demonstrate that the ECC used to repair defective cells can be combined with a simple architectural technique, which can also fix particle-induced soft errors, without increasing ECC strength or processor runtime. View full abstract»

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  • Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis

    Page(s): 2337 - 2341
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    Synthesis of custom instruction processors from high-level application descriptions involves automated evaluation of data-flow subgraphs as custom instruction candidates. A subgraph S of a graph D , is convex if no two vertices of S are connected by a path in D that is not also in S. An algorithm for enumerating all convex subgraphs of a directed acyclic graph (DAG) under input, output, and forbidden vertex constraints was given by Pozzi, Atasu, and Ienne. We show that this algorithm makes no more than O(|V(D)|Nin+Nout+1) recursive calls, where |V(D)| is the number of vertices in D, and Nin and Nout are input and output constraints, respectively. Therefore, when Nin and Nout are constants, the algorithm is of polynomial complexity. Furthermore, a convex subgraph S is a maximal convex subgraph if it is not a proper subgraph of some other convex subgraph, assuming that both are valid under forbidden vertex constraints. The largest maximal convex subgraph is called the maximum convex subgraph. There exist popular algorithms that enumerate maximal convex subgraphs, which all have exponential worst-case time complexity. This work shows that although no polynomial-time maximal convex subgraph enumeration algorithm can exist, the related maximum convex subgraph problem can be solved in polynomial time. View full abstract»

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  • High Speed Architectures for Finding the First two Maximum/Minimum Values

    Page(s): 2342 - 2346
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    High speed architectures for finding the first two maximum/minimum values are of paramount importance in several applications, including iterative (e.g., turbo and low-density-parity-check) decoders. In this brief, stemming from a previous work, based on radix-2 solutions, we propose higher and mixed radix implementations that improve the architecture latency. Post place and route results on a 180-nm CMOS standard cell technology show that the proposed architectures achieve lower latency than radix-2 solutions with a moderate area increase. View full abstract»

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  • Rethinking the Wirelength Benefit of 3-D Integration

    Page(s): 2346 - 2351
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    To sustain the pace of integration density improvement, 3-D IC technology is hailed as a “Beyond Moore” driver. It has been demonstrated to have great potential to diminish footprint, reduce interconnect delay, promote system performance, decrease power consumption and facilitate integration of heterogeneous processes. Besides, it is commonly cited as a means of reducing lateral wirelength. Some early theoretical and experimental studies have also shown that 3-D IC can significantly reduce lateral wirelength. However, the effect of through-silicon via (TSV) area overhead on the wirelength has been largely overlooked. In this paper, we derive a mathematical upper bound on the wirelength benefit of placing a circuit in 3-D that takes the TSV area overhead into account. For a set of IBM placement benchmarks scaled to the 32 nm process, we show that 3-D integration cannot help to reduce the wirelength under current TSV technologies. View full abstract»

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  • A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation

    Page(s): 2351 - 2355
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    This brief discusses modeling of a high-voltage generator, including a charge pump circuit and a regulator for accelerating system-level simulations. Event-driven simulators become slow when hard switching frequently occurs to enable charge pump circuits even with a conventional model. A current mirror is added to the pump model and is connected to an output node of a comparator in the voltage detector to make every node in the feedback loop fully analog. Simulation results show that the simulation time for voltage generators' system is reduced by a factor of about 10 with an error of 5% in comparison with the conventional model. View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

    Page(s): 2356
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  • 2012 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 20

    Page(s): 2357 - 2388
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Page(s): C3
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
y.ismail@aucegypt.edu