Special Notice
IEEE Xplore is transitioning to HTTPS on 9 April 2018. Customer access via EZproxy will require version 6 or higher with TLS 1.1 or 1.2 enabled.
Review our EZproxy Upgrade Checklist to ensure uninterrupted access.

# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 27

Publication Year: 2012, Page(s):C1 - C4
| PDF (157 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2012, Page(s): C2
| PDF (40 KB)
• ### Towards Process Variation-Aware Power Gating

Publication Year: 2012, Page(s):1929 - 1937
Cited by:  Papers (3)
| | PDF (1332 KB) | HTML

This paper presents a power gating design that considers process variation for proper wakeup control. First, the surge current constraint is examined and refined for a simpler and more realistic view of inter-module reliability. Following that, several circuits are proposed on top of a delay chain to adapt the timing control of power switches to process variations. Experimental results show that t... View full abstract»

• ### Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes

Publication Year: 2012, Page(s):1938 - 1950
Cited by:  Papers (28)
| | PDF (2161 KB) | HTML

Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. This paper first proposes enhancemen... View full abstract»

• ### A Failure Prediction Strategy for Transistor Aging

Publication Year: 2012, Page(s):1951 - 1959
Cited by:  Papers (10)
| | PDF (1737 KB) | HTML

This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a sys... View full abstract»

• ### Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown

Publication Year: 2012, Page(s):1960 - 1973
Cited by:  Papers (8)
| | PDF (2787 KB) | HTML

Gate oxide breakdown is an important reliability issue that has been widely studied at the individual transistor level, but has seen very little work at the circuit level. We first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to this phenomenon. The new approach accounts for the fact that not every breakdown leads to circuit failure, and sho... View full abstract»

• ### Tracking On-Chip Age Using Distributed, Embedded Sensors

Publication Year: 2012, Page(s):1974 - 1985
Cited by:  Papers (3)
| | PDF (2030 KB) | HTML

Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by... View full abstract»

Publication Year: 2012, Page(s):1986 - 1996
Cited by:  Papers (10)
| | PDF (1454 KB) | HTML

In this work, we propose a method to reduce the impact of process variations by adapting the application's algorithm at the software layer. We introduce the concept of hardware signatures as the measured post manufacturing hardware characteristics that can be used to drive software adaptation across different die. Using H.264 encoding as an example, we demonstrate significant yield improvements (a... View full abstract»

• ### Formal-Analysis-Based Trace Computation for Post-Silicon Debug

Publication Year: 2012, Page(s):1997 - 2010
Cited by:  Papers (4)  |  Patents (1)
| | PDF (1784 KB) | HTML

This paper presents a post-silicon debug methodology that provides a means to rewind, or backspace, a chip from a known crash state using a combination of on-chip real-time data collection and off-chip formal analysis methods. A complete debug flow is presented that considers practical considerations such as area, on-chip non-determinism and signal propagation delay. This flow, along with a low-ov... View full abstract»

• ### Optimizing Video Application Design for Phase-Change RAM-Based Main Memory

Publication Year: 2012, Page(s):2011 - 2019
Cited by:  Papers (8)
| | PDF (1679 KB) | HTML

Video applications including video codecs place a large traffic demand on main memory. Emerging memory technology, such as phase-change RAM (PRAM) tends to suffer from the write endurance problem, in which the maximum number of writes is limited. Thus, it is required to improve video application designs to adapt to the new requirements of emerging memory technology, i.e., to minimize the number of... View full abstract»

• ### Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory

Publication Year: 2012, Page(s):2020 - 2030
Cited by:  Papers (19)  |  Patents (1)
| | PDF (2205 KB) | HTML

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability, and simplicity of cell structure. However, large process variations of both magnetic tunneling junction (MTJ) and CMOS process severely limit the yield of STT-RAM chips and prevent the massive production from happening. In... View full abstract»

• ### Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors

Publication Year: 2012, Page(s):2031 - 2043
Cited by:  Papers (6)
| | PDF (1424 KB) | HTML

This paper presents a systematic approach to the design of application-specific instruction-set processors for high speed computation of local neighborhood functions and intra-field deinterlacing. The intended application is real-time processing of high definition video. The approach aims at an efficient utilization of the available memory bandwidth by fully exploiting the data parallelism inheren... View full abstract»

• ### A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

Publication Year: 2012, Page(s):2044 - 2053
Cited by:  Papers (34)
| | PDF (2926 KB) | HTML

Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area occupation, and CMOS process compatibility. One of the representative research areas for the spintronics logic is the zero standby leakage retention fl... View full abstract»

• ### Boolean Functions Over Nano-Fabrics: Improving Resilience Through Coding

Publication Year: 2012, Page(s):2054 - 2065
Cited by:  Papers (1)
| | PDF (1205 KB) | HTML

This paper determines mechanisms to mitigate errors when implementing Boolean functions in nano-circuits. Nano-fabrics are expected to have high defect rates as atomic variations directly impact such materials. This paper develops a coding mechanism that uses a combination of cheap, but unreliable nano-device as the main function and reliable, but expensive CMOS devices to implement the coding mec... View full abstract»

• ### Distributed TSV Topology for 3-D Power-Supply Networks

Publication Year: 2012, Page(s):2066 - 2079
Cited by:  Papers (14)  |  Patents (1)
| | PDF (2605 KB) | HTML

3-D integration has the potential to increase performance and decrease energy consumption. However, there are many unsolved issues in the design of these systems. In this work we study the design of 3-D power supply networks and demonstrate a technique specific to 3-D systems that improves IR-drop and dynamic noise over a straightforward extension of traditional design techniques. Previous work in... View full abstract»

• ### Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks

Publication Year: 2012, Page(s):2080 - 2093
Cited by:  Papers (2)
| | PDF (2259 KB) | HTML

The increasing viability of 3-D silicon integration technology has opened new opportunities for chip architecture innovations. One direction is in the extension of 2-D mesh-based tiled chip-multiprocessor architectures into three dimensions. This paper focuses on efficient routing algorithms for such 3-D mesh networks. Existing routing algorithms suffer from either poor worst-case throughput (DOR,... View full abstract»

• ### Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Publication Year: 2012, Page(s):2094 - 2103
Cited by:  Papers (11)
| | PDF (1379 KB) | HTML

Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology ... View full abstract»

• ### Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations

Publication Year: 2012, Page(s):2104 - 2117
Cited by:  Papers (9)
| | PDF (3323 KB) | HTML

State-of-the-art timing tools are built around the use of current source models (CSMs), which have proven to be fast and accurate in enabling the analysis of large circuits. As circuits become increasingly exposed to process and temperature variations, there is a strong need to augment these models to account for thermal effects and for the impact of adaptive body biasing, a compensatory technique... View full abstract»

• ### A Nonbinary LDPC Decoder Architecture With Adaptive Message Control

Publication Year: 2012, Page(s):2118 - 2122
Cited by:  Papers (3)
| | PDF (191 KB) | HTML

A new decoder architecture for nonbinary low-density paritycheck (LDPC) codes is presented in this paper to reduce the hardware operational complexity in VLSI implementations. The low decoding complexity is achieved by employing adaptive message control (AMC) that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. To implem... View full abstract»

• ### Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers

Publication Year: 2012, Page(s):2123 - 2127
| | PDF (433 KB) | HTML

This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing t... View full abstract»

• ### A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family

Publication Year: 2012, Page(s):2128 - 2132
Cited by:  Papers (8)
| | PDF (269 KB) | HTML

This paper investigates the design of a data flip-flop compatible with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption, an additional discharge phase is pe... View full abstract»

• ### Dynamic Power Management for the Iterative Decoding of Turbo Codes

Publication Year: 2012, Page(s):2133 - 2137
Cited by:  Papers (4)
| | PDF (355 KB) | HTML

Turbo codes are presently ubiquitous in the context of mobile wireless communications among other application domains. A decoder for such codes is typically the most power intensive component in the baseband processing chain of a wireless receiver. The iterative nature of these decoders represents a dynamic workload. This brief presents a dynamic power management policy for these decoders. An algo... View full abstract»

• ### Non-Uniform Coverage by $n$-Detection Test Sets

Publication Year: 2012, Page(s):2138 - 2142
Cited by:  Papers (2)
| | PDF (271 KB) | HTML

The use of n-detection test sets increases the likelihood of defect detection. With a uniform value of for all the target faults, the expectation is that defects across the circuit will be covered uniformly. This paper demonstrates that this may not be the case by considering the four-way bridging faults detected by n-detection test sets for single stuck-at faults in benchmark circuits. Partitioni... View full abstract»

• ### Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization

Publication Year: 2012, Page(s):2143 - 2147
Cited by:  Papers (13)
| | PDF (265 KB) | HTML

As technology scales, negative bias temperature instability (NBTI) has become a major reliability concern for circuit designers. And the growing process variations can no longer be ignored. Meanwhile, reducing power consumption remains to be one of the design goals. In this paper, a variation-aware supply voltage assignment (SVA) technique combining dual Vdd assignment and dynamic V View full abstract»

• ### Direct Compare of Information Coded With Error-Correcting Codes

Publication Year: 2012, Page(s):2147 - 2151
Cited by:  Papers (2)
| | PDF (352 KB) | HTML

There are situations in a computing system where incoming information needs to be compared with a piece of stored data to locate the matching entry, e.g., cache tag array lookup and translation look-aside buffer matching. If the stored data is protected with error-correcting codes (ECC) for reliability reason, the previous solution is to access the stored information, decode and correct if necessa... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu