# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 46

Publication Year: 2012, Page(s):C1 - 2002
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2012, Page(s): C2
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• ### Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm

Publication Year: 2012, Page(s):2003 - 2010
Cited by:  Papers (14)
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ON-current (Ion) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis. Variation sources of Ion are successfully extracted as independent contributions of threshold voltage Vt, transconductance Gm, and parasitic resistance Rpara. As well as Vt variability, Gm variation ex... View full abstract»

• ### Design of Novel High-$Q$-Factor Multipath Stacked On-Chip Spiral Inductors

Publication Year: 2012, Page(s):2011 - 2018
Cited by:  Papers (13)  |  Patents (2)
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High-Q-factor and small-occupying-area inductors are prerequisite for monolithic-microwave integrated-circuit applications. This paper presents a novel multipath crossover-interconnection octagon stacked spiral inductor which is fabricated with the 0.13-μm SiGe BiCMOS process. The metal wire of the spiral inductor is divided into multiple paths according to the process rule and the depth of... View full abstract»

• ### BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Publication Year: 2012, Page(s):2019 - 2026
Cited by:  Papers (38)  |  Patents (1)
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In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of... View full abstract»

• ### Probing the Interface Barriers of Dopant-Segregated Silicide–Si Diodes With Internal Photoemission

Publication Year: 2012, Page(s):2027 - 2032
Cited by:  Papers (4)
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An experimental study is presented to probe the interface barriers of dopant-segregated silicide-Si diodes with internal photoemission. The spatial information of the interface dipoles, which is believed to be the cause of the effective Schottky barrier height (SBH) modification, is extracted from the field dependence of the barrier heights. A clear difference between the dopant segregation (DS) j... View full abstract»

• ### Additional Nitrogen Ion-Implantation Treatment in STI to Relax the Intrinsic Compressive Stress for n-MOSFETs

Publication Year: 2012, Page(s):2033 - 2036
Cited by:  Papers (5)
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Based on the stress extraction and measurement by the atomic-force-microscope-Raman technique with nanometer-level space resolution, the high compressive stress about 700 MPa on the Si critical dimension (CD) is observed in the current complementary metal-oxide-semiconductor (CMOS) transistor. The difference of thermal expansion between Si and Shallow trench isolation (STI) oxide during the total ... View full abstract»

• ### Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

Publication Year: 2012, Page(s):2037 - 2041
Cited by:  Papers (33)
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We present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of SRAM. Using a taller fin FinFET for the pull-down device increases the read static noise margin of the SRAM and can potentially reduce the SRAM cell area. A reasonable amount of channel doping in all the transistors can be used to reduce the c... View full abstract»

• ### Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

Publication Year: 2012, Page(s):2042 - 2048
Cited by:  Papers (45)
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New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapp... View full abstract»

• ### Evidence for Voltage-Driven Set/Reset Processes in Bipolar Switching RRAM

Publication Year: 2012, Page(s):2049 - 2056
Cited by:  Papers (70)
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Understanding the physical mechanisms for resistance change in metal oxides is a key challenge to assess the scalability of resistive-switching random access memory (RRAM) devices. From this standpoint, the time dependence of filament formation and dissolution in metal oxides can provide a useful insight into the fundamental mechanism of resistive switching. In this paper, we show an experimental ... View full abstract»

• ### Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies

Publication Year: 2012, Page(s):2057 - 2063
Cited by:  Papers (20)
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The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current) when subjected to fin roughness up to 1 nm root-me... View full abstract»

• ### Material Selection for Minimizing Direct Tunneling in Nanowire Transistors

Publication Year: 2012, Page(s):2064 - 2069
Cited by:  Papers (26)
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When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon n... View full abstract»

• ### Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

Publication Year: 2012, Page(s):2070 - 2077
Cited by:  Papers (36)
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We investigate a promising tunnel FET configuration having a gate on the source only, which is simultaneously exhibiting a steeper subthreshold slope and a higher ON-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based on a recently developed 2-D quantum-mechanical simulator calculating band-to-band tunneling and including quantum confinement... View full abstract»

• ### Novel Concept of the Three-Dimensional Vertical FG nand Flash Memory Using the Separated-Sidewall Control Gate

Publication Year: 2012, Page(s):2078 - 2084
Cited by:  Papers (9)
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Recently, we proposed a novel 3-D vertical floating gate (FG)-type nand Flash memory cell array using the separated-sidewall control gate (CG) (S-SCG). This novel cell consists of one cylindrical FG with line-type CG and S-SCG structures. For simplifying the process flow, we realized the common S-SCG lines by using the prestacked polysilicon layer, through which variable medium voltages are applie... View full abstract»

• ### Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

Publication Year: 2012, Page(s):2085 - 2092
Cited by:  Papers (58)
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This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal o... View full abstract»

• ### Characterization and Modeling of Hot Carrier-Induced Variability in Subthreshold Region

Publication Year: 2012, Page(s):2093 - 2099
Cited by:  Papers (6)
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We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensiv... View full abstract»

• ### A Distributed Bulk-Oxide Trap Model for $hbox{Al}_{2} hbox{O}_{3}$ InGaAs MOS Devices

Publication Year: 2012, Page(s):2100 - 2106
Cited by:  Papers (70)
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This paper presents a distributed circuit model for bulk-oxide traps based on tunneling between the semiconductor surface and trap states in the gate dielectric film. The model is analytically solved at dc. It is shown that the distributed bulk-oxide trap model correctly depicts the frequency dispersion in the capacitance- and conductance-voltage data of Al2O3-InGaAs MOS devi... View full abstract»

• ### Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm)

Publication Year: 2012, Page(s):2107 - 2114
Cited by:  Papers (51)
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The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials t... View full abstract»

• ### Slow Detrapping Transients due to Gate and Drain Bias Stress in High Breakdown Voltage AlGaN/GaN HEMTs

Publication Year: 2012, Page(s):2115 - 2122
Cited by:  Papers (24)
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Charge trapping and slow (from 10 s to >; 1000 s) detrapping in AlGaN/GaN high electron mobility transistors (HEMTs) designed for high breakdown voltages ( >; 1500 V) is studied through a combination of electrical, thermal, and optical methods to identify the impact of Al molefraction and passivation on trapping. Trapping due to 5-10 V drain bias stress in the on-state (Vgs = 0) i... View full abstract»

• ### Calculation of the Nonlinear Junction Temperature for Semiconductor Devices Using Linear Temperature Values

Publication Year: 2012, Page(s):2123 - 2128
Cited by:  Papers (9)
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The drive for smaller, faster, and higher output power integrated circuits continues to push the device junction (channel) temperature to higher levels. An accurate estimate of the maximum junction temperature is necessary for ensuring proper and reliable operation. In most cases, for simplicity, the thermal resistance within the device is calculated or measured assuming constant thermal conductiv... View full abstract»

• ### Some Failure Mechanisms in Charge-Sensitive Infrared Phototransistors

Publication Year: 2012, Page(s):2129 - 2135
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For an infrared photon detector, such as charge-sensitive infrared phototransistors (CSIPs), we propose and use a capacitive charging method to study some failure mechanisms that disable the photon response of CSIPs. Two failure mechanisms are highlighted, namely interquantum well (QW) leakage and low tunneling probability for intersubband-transition-excited electrons. A correlation between the Al... View full abstract»

• ### Improvement of RF and Noise Characteristics Using a Cavity Structure in InAlAs/InGaAs HEMTs

Publication Year: 2012, Page(s):2136 - 2141
Cited by:  Papers (7)  |  Patents (1)
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Reduction of parasitic capacitance in the gate region by adopting a cavity structure improved the high-frequency and noise characteristics of InAlAs/InGaAs high-electron mobility transistors (HEMTs). We achieved a high cutoff frequency fT of 517 GHz and a minimum noise figure NFmin of 0.71 dB at 94 GHz even after passivation and interconnection process. Scaling of the gate-to... View full abstract»

• ### Implementation of an a-Si:H TFT Gate Driver Using a Five-Transistor Integrated Approach

Publication Year: 2012, Page(s):2142 - 2148
Cited by:  Papers (16)
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An integrated five-transistor/one-capacitor approach for realizing a a-Si:H thin-film transistor (TFT) gate driver operating in multiphase-clock mode is proposed and investigated. The driver needs only one large-size TFT and one small-size storage capacitor. The performance and function of the proposed driver are verified experimentally. The dependence of the performance on the device size is stud... View full abstract»

• ### The Effects of Dual-Active-Layer Modulation on a Low-Temperature Solution-Processed Oxide Thin-Film Transistor

Publication Year: 2012, Page(s):2149 - 2152
Cited by:  Papers (13)
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We applied dual-active-layer (DAL) modulation to solution-processed AlInZnO (AIZO)/InZnO (IZO) DAL thin-film transistors (TFTs) to realize high performance at 350°C. The electrical characteristics of the DAL TFTs were affected by the In-versus-Zn ratio of each channel and the thickness of the IZO. This caused a difference in the carrier concentrations of the two channels and also changed th... View full abstract»

• ### Design Rules for IGZO Logic Gates on Plastic Foil Enabling Operation at Bending Radii of 3.5 mm

Publication Year: 2012, Page(s):2153 - 2159
Cited by:  Papers (22)
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Findings obtained from bending experiments with mechanically flexible InGaZnO-based thin-film transistors are used to derive design rules for flexible InGaZnO-based n-channel metal-oxide-semiconductor logic circuits. Based on the developed design rules, flexible NAND gates, inverters, and five-stage ring oscillators are fabricated directly on free-standing plastic foils at temperatures ≤ 15... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy