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Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug. 2012

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Displaying Results 1 - 20 of 20
  • Table of contents

    Page(s): C1
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1797
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  • Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference

    Page(s): 1798 - 1799
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  • Complete SOC Transceiver in 0.18 \mu m CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking

    Page(s): 1800 - 1809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2057 KB) |  | HTML iconHTML  

    Portable audio products have not yet seen a wireless headphone solution that has been widely accepted. The main reason for this is that power consumption for current solutions is too high. We present a solution the uses a sub-sampling receiver combined with Q-enhanced RF filtering and injection-locked LO generation to provide high performance with low power consumption. This paper describes in detail the transceiver architecture, frequency plan, tuning algorithms and obtained performance. The transceiver is fabricated in TSMC 0.18 μm CMOS. The analog and RF sections of the transceiver consume peak currents of 5.2 mA in RX mode and 20.3 mA in TX mode. View full abstract»

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  • A Transformer-Based Broadband Front-End Combo in Standard CMOS

    Page(s): 1810 - 1819
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    This paper presents a broad band front-end combo scheme based on a three-way on-chip transformer. The combo scheme functions as the T/R switch, balun, and impedance matching network simultaneously. A design example implemented in a standard 90 nm CMOS process demonstrates a 2 GHz 1-dB bandwidth from 5 GHz to 7 GHz. During the transmitting (TX) mode, the reported design achieves 2.65 dB insertion loss, +45.7 dBm IIP3, and 42 dB antenna-to-receiver isolation; in the receiving (RX) mode, the design demonstrates 2.52 dB insertion loss, +44.2 dBm IIP3, and 42 dB antenna-to-transmitter isolation. The TX-to-RX isolation is kept below 50 dB. The front-end combo design occupies a compact core area of 0.5 mm2 which includes the on-chip transformer. View full abstract»

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  • A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

    Page(s): 1820 - 1827
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    A series combining transformer(SCT)-based, watt-level 1.9 GHz linear CMOS power amplifier with an on-chip linearizer is demonstrated. Proposed compact, predistortion-based linearizer is embedded in the two-stage PA to compensate AM-PM distortion of the cascode power stages, and improve ACLR of 3GPP WCDMA uplink signal by 2.6 dB at 28.0 dBm output power. The designed interstage power distributor with one tuning inductor contributes to low-loss power supply for the driver stage and high common-mode stability of the whole PA. Moreover, a newly developed PVT variation- tolerant cascode biasing circuit guarantees highly accurate bias voltages in a wide supply voltage range from 2.5 V to 3.6 V. The test chip demonstrates maximum output power of 28.3 dBm at 1.95 GHz, satisfying 3GPP WCDMA spectrum mask with die area of 5.4 mm2. View full abstract»

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  • A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

    Page(s): 1828 - 1841
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    This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16 GFC and consumes 385 m W/link. View full abstract»

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  • 0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

    Page(s): 1842 - 1853
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    A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a per-data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER <; 10-12 across a 20-cm FR4 PCB channel. View full abstract»

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  • A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

    Page(s): 1854 - 1865
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    A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC. View full abstract»

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  • A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

    Page(s): 1866 - 1883
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    A dynamic comparator-based OTA is introduced as a replacement for a conventional OTA. It performs charge transfer in a switched-capacitor circuit by repeatedly evaluating the polarity of the differential input using a dynamic clocked comparator and injecting current pulses at the output to move the input voltage toward zero. The amplitude of the current pulse is reduced each time the input voltage crosses zero to provide fast but accurate settling of the output voltage. Dynamic comparator-based OTAs are applied to the design of a 1-1-1-1 MASH delta-sigma modulator. The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using zero-crossing-based circuits or comparator-based switched capacitors. Because of the dynamic operation of the OTAs and discrete-time delta-sigma modulator architecture, both bandwidth and power consumption linearly scale with the sampling frequency without any reconfiguration of the modulator. View full abstract»

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  • A 16 MHz BW 75 dB DR CT \Delta \Sigma ADC Compensated for More Than One Cycle Excess Loop Delay

    Page(s): 1884 - 1895
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    The maximum sampling rate of a continuous-time ΔΣ modulator in a given process is limited by the minimum flash ADC delay that can be realized. Excess loop delay compensation techniques that are widely used can compensate for delays up to half a clock cycle. Addition of a fast loop outside the flash ADC can break this limit and compensate for one and half clock cycles of delay at the cost of reducing the order of noise shaping by one. This technique, along with a low latency flash ADC, and a delay free calibrated DAC, result in a lowpass continuous-time ΔΣ ADC with the highest reported sampling rate in a 0.18 m process. The prototype occupies 0.68 mm2 , consumes 47.6 mW, and operates at 800 MS/s. In a 16 MHz bandwidth (oversampling ratio of 25), the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 75 dB, 67 dB, and 65 dB respectively. In a 32 MHz bandwidth, the dynamic range, maximum signal to noise ratio, and maximum signal to noise and distortion ratios are 64 dB, 57 dB, and 57 dB, respectively. View full abstract»

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  • A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices

    Page(s): 1896 - 1907
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    An ultra-low-power, low-voltage frequency synthesizer designed for implantable medical devices is presented. Several design techniques are adopted to address the issues in ultra-low voltage and current design. The charge pump (CP) in the synthesizer utilizes dynamic threshold-voltage and switch-coupled techniques to provide a high driving current with a low standby current. The synthesizer adopts a ring-based voltage controlled oscillator (VCO) that utilizes a dual resistor-varactor tuning technique to compensate for process-voltage-temperature (PVT) variations and the exponential voltage-to-current curve. Implemented in a 0.13-μm CMOS technology, the 0.5-V medical-band frequency synthesizer consumes 440 μW while exhibiting a phase noise of 91.5 dBc/Hz at 1-MHz frequency offset. View full abstract»

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  • A Dither-Less All Digital PLL for Cellular Transmitters

    Page(s): 1908 - 1920
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    An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of -108 dBc/Hz, an out-of-band phase noise of -160 dBc/Hz @20 MHz and in-band fractional spurs below -50 dBc. These results are obtained for an output carrier of 1.8 GHz, a reference clock of 26 MHz, with a power consumption of 41.6 mW. View full abstract»

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  • A 60 mW Class-G Stereo Headphone Driver for Portable Battery-Powered Devices

    Page(s): 1921 - 1934
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    A 60 mW 1.15 mA/channel Class-G stereo headphone driver primarily designed for demanding applications in mobile phones and other portable communication devices is described. The architecture of the driver has been chosen to overcome the various design challenges for audio amplifiers in a wireless environment. A high-order feed-forward loop topology provides high immunity to battery disturbance with extended correction range. In addition, a Class-G amplifier with a Class-AB/B driving stage improves the small-signal efficiency and extends music playback time. Implemented in 0.18 μm CMOS technology, the stereo headphone driver achieves a DR of 111 dB and PSRR of 120 dB at the GSM TDMA frequency of 217 Hz while occupying an area of 2.3 mm2. View full abstract»

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  • A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI

    Page(s): 1935 - 1945
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    A four-phase integrated buck converter in 45 nm silicon-on-insulator (SOI) technology is presented. The controller uses unlatched pulse-width modulation (PWM) with nonlinear gain to provide both stable small-signal dynamics and fast response (~700 ps) to large input and output transients. This fast control approach reduces the required output capacitance by 5× in comparison to a conventional, latched PWM controller at a similar operating point. The converter switches package-integrated air-core inductors at 80 MHz and delivers 1 A/mm2 at 83% efficiency and 0.66 conversion ratio. A network-on-chip (NoC) serves as a realistic digital load along with a programmable current source capable of generating load current steps with slew rate of ~1 A/100 ps for characterization of the control scheme. View full abstract»

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  • Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS

    Page(s): 1946 - 1959
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    This paper describes design considerations for a digital inductive-switching DC/DC converter suitable for direct battery connection in a deep sub-micron CMOS process. Digital control techniques and robust circuit design methods take advantage of the advanced process technology while avoiding the barriers to direct battery connection and high efficiency, high power density voltage conversion. The approach is verified on a prototype converter, implemented in 40 nm standard bulk CMOS. The design achieves a peak efficiency of 95% for an input range of up to 5.5 V. The transient response is optimized for typical mobile SoC operating conditions and achieves step response times as fast as 35 μs/V under load. View full abstract»

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  • ISSCC 2013 conference theme 60 years of em powering the future

    Page(s): 1960
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  • IEEE Journal of Solid-State Circuits information for authors

    Page(s): C3
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  • [Blank page - Back cover]

    Page(s): C4
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan