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Design & Test of Computers, IEEE

Issue 2 • Date April 2012

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Displaying Results 1 - 25 of 33
  • [Front cover]

    Page(s): C1
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  • IEEE Xplore Digital Library [advertisement]

    Page(s): C2
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  • IEEE Design & Test of Computers publication information

    Page(s): 1
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  • Table of contents

    Page(s): 2
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  • Departments

    Page(s): 3
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  • Standards, Interoperability, and Innovation in a Disaggregated IC Industry

    Page(s): 4
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  • Guest Editors' Introduction: Special Issue on EDA Industry Standards

    Page(s): 5 - 7
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  • Abstraction and Standardization in Hardware Design

    Page(s): 8 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    Levels of abstraction in design are explained in a very easy-to-understand style. Initially, the article focuses on the mechanics behind the abstraction principles and abstraction levels in the electronic design. It also takes into account the effect technology development has on the evolution of abstraction. Abstractions such as RTL, TLM and high-level design are reviewed. View full abstract»

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  • An Overview of Open SystemC Initiative Standards Development

    Page(s): 14 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    This article describes the major motivation for development of SystemC standards and provides a good overview of the same. The six working groups are described. System designers, especially those with a background in System Verilog can gain a good basic understanding of system verification using System C. As such it can be a stepping stone to building a bridge between SystemC and System Verilog. View full abstract»

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  • SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience

    Page(s): 23 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    This paper provides insight into the development of System Verilog Assertions standardization efforts. Specifically it covers the evolution from Accellera 3.1a version to its current state of standardization (the upcoming SVA2012 release). Insight into the new features, changes and the reasons for the same exposes users of SVA to the direction the standard is evolving. View full abstract»

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  • Understanding the Accellera SCE-MI Transaction Pipes

    Page(s): 32 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1247 KB) |  | HTML iconHTML  

    Mixed platform for IP verification has become an increasingly important topic and the SCE-MI standard aims to solve communication issue between software and hardware parts of the platform. This paper is directed primarily towards infrastructure developers to better understand the SCE-MI standard. Different configurations of the transaction pipes are described. View full abstract»

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  • OpenAccess: Standard and Practices

    Page(s): 44 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (693 KB) |  | HTML iconHTML  

    This paper discusses the details of the OpenAccess API standard and reference database, such as, Embedded Module Hierarchy and oaConstraint class hierarchy through which foundry rules are represented in OpenAccess. It provides details on performance and discusses native support for multi-threading. Comparative results are presented on the merits of compressing the database. It also discusses the OpenAccess standardization process and levels of compatibility between releases that are part of the standardization approach. View full abstract»

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  • Interoperable Design Constraints for Custom IC Design

    Page(s): 53 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (467 KB) |  | HTML iconHTML  

    This paper presents the details of analog design constraints that are defined to enable interoperability between analog tools from different providers. They are focused on the implementation phase of a design to enable automatic layout generation. These constraints are based on OpenAccess and are design specific, as opposed to process constraints that are defined by the semiconductor manufacturers. This paper discusses the underlying requirements for this standard and also provides examples of the representations of some of the constraints in OpenAccess. View full abstract»

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  • Low-Power Design Using the Si2 Common Power Format

    Page(s): 62 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    This paper covers details of the Common Power Format (CPF) standard which is used for expressing power intent for IC design to minimize power consumption. It presents the key underlying concepts in the standard, such as, power domains and power nodes. It provides a simple example to show how power intent is expressed. It then discusses how power intent can be expressed in a layered manner to cover the entire design process as well as support for hierarchy in design. It elaborates on how IC's are designed using CPF and touches on key aspects of interoperability with the IEEE1801 low power standard. View full abstract»

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  • Leakage Power Contributor Modeling

    Page(s): 71 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (430 KB) |  | HTML iconHTML  

    Low-power or power-aware design is one of the greatest challenges facing the semiconductor industry. The fidelity of low power design is dependent on the accuracy of power modeling across a wide range of PVT values. This paper describes an alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability of power consumption for different portions of a cell. An experimental use of this approach is also presented that demonstrates how the effort to characterize leakage power can be greatly reduced with only a marginal impact on accuracy. View full abstract»

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  • Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687

    Page(s): 79 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1139 KB) |  | HTML iconHTML  

    This paper discusses the reuse and retargeting of test instruments and test patterns using the IEEE P1687 standard in an era where reuse of existing functional elements and integration of IP blocks is accelerating rapidly. It briefly discusses the deficiencies of existing 1149.1 (JTAG) and 1500 standards and demonstrates how the new standard, P1687, plugs these exposures by specifying JTAG as an off-chip to on-chip interface to the instrument access infrastructure. It provides a simple example to underscore the need for the standard and then builds on this example to show how the standard can be used for more complex situations. View full abstract»

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  • Standards and Collaboration Perspectives: Yesterday, Today, and Tomorrow [Perspectives]

    Page(s): 89 - 92
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  • IEEE Xplore Digital Library [advertisement]

    Page(s): 93
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  • Call for papers

    Page(s): 94
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  • IEEE Xplore Digital Library [advertisement]

    Page(s): 95
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  • Too Much Automation?

    Page(s): 96 - 98
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  • IEEE Xplore Digital Library [advertisement]

    Page(s): 99
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  • Managing complex boundary-scan operations

    Page(s): 100 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    The IEEE 1149.1 Standard for Test Access Port and Boundary-Scan Architecture was approved and released in 1990. Since that time, there have been two supplements and one revision to the standard. A second revision is currently in process. The 1149.1 standard was originally developed to address board level test access issues while at the same time enabling access to test logic inside the device. As technology has scaled over the last 20+ years, component and board level density and complexity have grown significantly. A new class of defects (Timing, Power, Signal Integrity) has also become more prevalent and much more difficult to detect. View full abstract»

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  • IEEE Xplore Digital Library [advertisement]

    Page(s): 103
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  • IEEE Design and Test Call for Papers: Special Issue on Practical Parallel EDA [CEDA Currents]

    Page(s): 104 - 105
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty