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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 7 • Date July 2012

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Displaying Results 1 - 21 of 21
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

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  • Demonstration of a Low-Cost Ultrawideband Transmitter in the 3.1–10.6-GHz Band

    Page(s): 389 - 393
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (766 KB) |  | HTML iconHTML  

    An architecture for the generation of short pulses based on a filter step response technique is described. One uses the transient response of a passive circuit to an input square signal. This approach is experimentally demonstrated by the generation of subnanosecond pulses compatible with the indoor frequency mask authorized by the Federal Communications Commission for ultrawideband applications. It is shown that a pulse repetition frequency of 1 GHz can be achieved. The effect of the transition time of the source is analyzed and is shown not to be a limitation. View full abstract»

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  • Ultralow-Power Ku-Band Dual-Feedback Armstrong VCO With a Wide Tuning Range

    Page(s): 394 - 398
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (682 KB) |  | HTML iconHTML  

    Here, we investigate the design of a Ku-band Armstrong voltage-controlled oscillator (VCO) utilizing dual transformer feedback for low-voltage low-power operation. The primary transformer feedback between the drain and the source of the VCO increases the output voltage swing under low supply voltage. With the secondary transformer feedback, g_m-boosting is obtained by the coupling between the drain and the gate of the Armstrong VCO. Combined with transformer feedback, g_m-boosting further reduces the negative transconductance required for oscillation startup, enabling ultralow-power operation. Thus, the proposed Armstrong VCO with dual feedback operates at 0.4 V with power consumption as low as 600 W. Under this condition, the measured phase noise of the VCO is -100.6 dB/Hz at 1-MHz offset from a 14.1-GHz carrier. The results show that the proposed VCO is suitable for very low-power applications requiring high signal purity. View full abstract»

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  • Broad-Band Odd-Number CMOS Prescalers With Quadrature/Symmetrical Outputs

    Page(s): 399 - 403
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (591 KB) |  | HTML iconHTML  

    In this brief we present two architectures for digital division by odd numbers suitable for implementation in high-speed prescalers. First, we show a technique that delivers accurate in-phase and quadrature outputs over a wide frequency range from an inherently symmetrical circuit structure, which is particularly suited to the realization of image-rejection transceiver architectures with offset local oscillator frequency. The second technique focuses on generating precise 50% duty cycle outputs, which are intended for direct mixer drive to achieve low output dc offset and second-order input intercept point. Both concepts can be realized in a wide range of logic forms. Demonstrator circuits implemented in high-speed current-mode logic have been fabricated in 0.18-m digital CMOS technology, and both techniques show robust odd-number division. The test chips consume approximately 7 mA each from a 1.8-V supply. View full abstract»

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  • A Method for the Schmitt-Trigger Propagation-Delay Compensation in Asynchronous Sigma–Delta Modulator

    Page(s): 404 - 408
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB) |  | HTML iconHTML  

    This brief provides the mathematical analysis of the Schmitt-trigger propagation-delay influence on the asynchronous sigma-delta modulator (ASDM) output-signal frequency spectrum. Beside the propagation delay, the Schmitt-trigger slew-rate impact has been also presented. Based on the mathematical analysis, a method for the Schmitt-trigger propagation-delay compensation has been proposed. The method is implemented by introducing hysteresis-level modulation. The first-order ASDM simulation and measurement models have been proposed for the propagation-delay influence to the ASDM output-signal frequency and for the compensation method verification. The measurement and simulation results for the proposed method confirm the ASDM output frequency spectrum improvement. View full abstract»

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  • A CMOS Rectifier With a Cross-Coupled Latched Comparator for Wireless Power Transfer in Biomedical Applications

    Page(s): 409 - 413
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB) |  | HTML iconHTML  

    A highly efficient rectifier for wireless power transfer in biomedical implant applications is implemented using 0.18-m CMOS technology. The proposed rectifier with active nMOS and pMOS diodes employs a four-input common-gate-type capacitively cross-coupled latched comparator to control the reverse leakage current in order to maximize the power conversion efficiency (PCE) of the rectifier. The designed rectifier achieves a maximum measured PCE of 81.9% at 13.56 MHz under conditions of a low 1.5-Vpp RF input signal with a 1- k output load resistance and occupies 0.009 mm2 of core die area. View full abstract»

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  • A Direct Fast Feedback Current Driver Using an Inverting Amplifier for High-Quality AMOLED Displays

    Page(s): 414 - 418
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB) |  | HTML iconHTML  

    A direct fast feedback current (DFFC) driver is proposed for high-quality AMOLED displays with inverted type pixels. The driver is implemented using an integrator with a loop compensator and an inverting amplifier with a switchedcapacitor gain circuit. Demultiplexing operation is realized to drive two channels using one driver. The measurement result shows settling time of 7 μs for a panel load of 1.5 kΩ/100 pF. The driver is fabricated in a 0.35-μm CMOS process, and the area is 120 × 131 μm2 per two channels. View full abstract»

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  • Continuous-Time Analog Two-Dimensional IIR Beam Filters

    Page(s): 419 - 423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (783 KB) |  | HTML iconHTML  

    Analog filter circuits that are realized in continuous-time discrete-space domain are proposed for implementing 2-D infinite impulse response (IIR) spatiotemporal transfer functions having beam-shaped passbands. These filters may be used for analog beamforming applications including seismic, audio, sonar, and ultrasonic signal processing. Unlike digital implementations, the proposed 2-D analog beam filters avoid the need for A/D conversions and digital circuitry. Importantly, the beam distortion (beam squint) due to bilinear transformation that is unavoidable in digital 2-D IIR beam filters is significantly reduced. A demonstrative example using operational amplifiers for first-order analog filters is provided. View full abstract»

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  • An All-Digital Large- N Audio Frequency Synthesizer for HDMI Applications

    Page(s): 424 - 428
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    In this brief, a novel all-digital and large-frequency-multiplication-ratio audio frequency synthesizer for high-definition multimedia interface applications is presented. The proposed large- N frequency synthesizer is designed in an all-digital manner to reduce circuit complexity and design efforts in advanced CMOS process technology, as compared with prior studies. The proposed frequency synthesizer does not require an extra high-frequency reference clock source but employs a single locking loop to reduce lock-in time and enhance loop stability. Based on the proposed frequency search algorithm and the high-resolution digitally controlled oscillator, the frequency synthesizer cannot only provide a large frequency multiplication ratio, but it also achieves low-jitter performance. Measurement results show that the frequency multiplication ratio has a range of 4096 to 25 088 and that the power consumption of the proposed frequency synthesizer can be improved to 591 μW (at 24.576 MHz) with a peak-to-peak jitter of 1.23%. In addition, the proposed frequency synthesizer can be implemented with standard cells, making it easily portable to different processes and very suitable for system-on-a-chip applications. View full abstract»

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  • Design and Iso-Area V_{\min} Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

    Page(s): 429 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (820 KB) |  | HTML iconHTML  

    In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-W active power consumption. View full abstract»

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  • Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT

    Page(s): 434 - 438
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (882 KB) |  | HTML iconHTML  

    We have suggested a new data-access scheme for the computation of lifting two-dimensional (2-D) discrete wavelet transform (DWT) without using data transposition. We have derived a linear systolic array directly from the dependence graph (DG) and a 2-D systolic array from a suitably segmented DG for parallel and pipeline implementation of 1-D DWT. These two systolic arrays are used as building blocks to derive the proposed transposition-free structure for lifting 2-D DWT. The proposed structure requires only a small on-chip memory of (4N + 8P) words and processes a block of P samples in every cycle, where N is the image width. Moreover, it has small output latency of nine cycles and does not require control signals which are commonly used in most of the existing DWT structures. Compared with the best of the existing high-throughput structures, the proposed structure requires the same arithmetic resources but involves 1.5N less on-chip memory and offers the same throughput rate. ASIC synthesis result shows that the proposed structure for block size 8 and image size 512 512 involves 28% less area, 35% less area-delay product, and 27% less energy per image than the best of the corresponding existing structures. Apart from that, the proposed structure is regular and modular; and it can be easily configured for different block sizes. View full abstract»

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  • Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements

    Page(s): 439 - 442
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high- k/metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy. View full abstract»

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  • New Stability Criterion for Fixed-Point State-Space Digital Filters With Generalized Overflow Arithmetic

    Page(s): 443 - 447
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (157 KB) |  | HTML iconHTML  

    In this brief, a new criterion for the global asymptotic stability of fixed-point state-space digital filters using generalized saturation arithmetic is presented. Compared with some existing results, a distinct feature of the proposed criterion is that it can include the existing results as special cases or be less restrictive than them. Two examples are given to show this improvement over the existing conditions. View full abstract»

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  • Design of a High-Data-Rate Differential Chaos-Shift Keying System

    Page(s): 448 - 452
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    In a differential chaos-shift keying (DCSK) system, the reference and information chaotic bearing signals are transmitted in two consecutive time slots and require the presence of delay components in the modulator and demodulator circuits. This system design requires a difficult-to-implement radio-frequency delay line that limits the data rate. The code-shifted DCSK (CS-DCSK) system proposes a solution for these problems by spreading the two chaotic slots by Walsh codes instead of using a time delay and sending them during the same time interval. In this brief, we extend the study of the CS-DCSK system, and we design two versions of a high-data-rate CS-DCSK system, which increase the data rate and can also perform in a multiuser case. The idea to achieve a high data rate is to get the information bits to share the same reference chaotic slot, where their separation is assured and maintained by different chaotic signals. In addition, this new design is not limited to a restricted number of Walsh codes such as CS-DCSK and provides from the properties of the chaotic signal in terms of security and good correlation properties. Finally, the performances of the systems are analyzed. View full abstract»

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  • Lyapunov-Type Theorem of General Two-Dimensional Nonlinear Parameter-Varying FM Second Model

    Page(s): 453 - 457
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB) |  | HTML iconHTML  

    This brief is concerned with the Lyapunov-type stability theorem of general 2-D nonlinear parameter-varying Fornasini-Marchesini (FM) second model. First, three comparison lemmas are given and play an important role in the stability analysis. Then, it is shown that a general 2-D nonlinear parameter-varying FM second model is uniformly stable (or uniformly asymptotically stable and exponentially stable) if it admits a corresponding continuous Lyapunov-type function. View full abstract»

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  • ISCAS 2013

    Page(s): 458
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  • Special issue on ultra low voltage vlsicircuits and systems

    Page(s): 459
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

    Page(s): 460
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • [Blank pages - Back Covers]

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope