IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Aug. 2012

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2012, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2012, Page(s): C2
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  • MARS: Matching-Driven Analog Sizing

    Publication Year: 2012, Page(s):1145 - 1158
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6956 KB) | HTML iconHTML

    This paper presents a new approach for automatic computation of matching constraints for analog sizing. The method automatically analyzes a circuit netlist to generate sizing constraints. These sizing constraints are considered during a subsequent numerical optimization. It is the first method that computes symmetry constraints for sizing, based on the hierarchical structure of the circuit and a q... View full abstract»

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  • TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems

    Publication Year: 2012, Page(s):1159 - 1168
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2480 KB) | HTML iconHTML

    The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This urgently requires both power and thermal management during system design. In this paper, we propose a model checking-based technique using extended timed automata to solve the processor frequency assignment problem in a temperature and energy-constrained mult... View full abstract»

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  • FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis

    Publication Year: 2012, Page(s):1169 - 1179
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2330 KB) | HTML iconHTML

    An efficient filter synthesis algorithm is proposed to minimize the number of adders required in the design of finite-impulse response filters. Given a specification, a filter can be synthesized by conducting two main steps: coefficient generation and multiplier-block synthesis. While most of previous works have focused on only one of the steps, the proposed algorithm integrates the two steps in a... View full abstract»

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  • Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control

    Publication Year: 2012, Page(s):1180 - 1193
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4823 KB) | HTML iconHTML

    We propose an explicit numerical integration method based on matrix exponential operator for transient analysis of large-scale circuits. Solving the differential equation analytically, the limiting factor of maximum time step changes largely from the stability and Taylor truncation error to the error in computing the matrix exponential operator. We utilize Krylov subspace projection to reduce the ... View full abstract»

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  • TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

    Publication Year: 2012, Page(s):1194 - 1207
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (22259 KB) | HTML iconHTML

    In this paper, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3-D integrated circuits (ICs). First, we analyze detailed thermomechanical stress induced by through-silicon vias in conjunction with various associated structures such as landing pad and dielectric lin... View full abstract»

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  • An Analytical Placer for VLSI Standard Cell Placement

    Publication Year: 2012, Page(s):1208 - 1221
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7512 KB) | HTML iconHTML

    Placement is the process of determining the exact locations of circuit elements within a chip. It is a crucial step in very large scale integration (VLSI) physical design, because it affects routability, performance, and power consumption of a design. In this paper, we develop a new analytical placer to solve the VLSI standard cell placement problem. The placer consists of two phases, multilevel g... View full abstract»

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  • Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits

    Publication Year: 2012, Page(s):1222 - 1234
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (17701 KB) | HTML iconHTML

    This paper presents a design methodology for robust and low-energy clock networks for ultralow voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (Fmax) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware met... View full abstract»

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  • A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs

    Publication Year: 2012, Page(s):1235 - 1248
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8784 KB) | HTML iconHTML

    The rapid scaling of silicon technology has enabled massive transistor integration densities. Nanometer feature sizes, however, are marred by increasing variability and susceptibility to wear-out. Billion-transistor designs, such as chip multiprocessors (CMPs), are especially vulnerable to defects. CMPs rely on a network-on-chip for all their communication needs. A single link failure within this ... View full abstract»

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  • Automatic TLM Fault Localization for SystemC

    Publication Year: 2012, Page(s):1249 - 1262
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3612 KB) | HTML iconHTML

    To meet today's time-to-market demands, catching bugs as early as possible during the design of a system is essential. In electronic system level design where SystemC has become the de-facto standard due to transaction level modeling (TLM), many approaches for verification have been developed. They determine an error trace that demonstrates the difference between the required and the actual behavi... View full abstract»

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  • On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation

    Publication Year: 2012, Page(s):1263 - 1274
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4676 KB) | HTML iconHTML

    Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification. One effective silicon debug technique is to monitor and trace the behaviors of the circuit during its normal operation. However, due to the associated overhead, designers can only afford to trace a small number of signals in the design. Selecting whic... View full abstract»

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  • Testability-Driven Statistical Path Selection

    Publication Year: 2012, Page(s):1275 - 1287
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2655 KB) | HTML iconHTML

    In the face of large-scale process variations, statistical timing methodology has advanced significantly over the last few years, and statistical path selection takes advantage of it in at-speed testing. In deterministic path selection, the separation of path selection and test generation is known to require time consuming iteration between the two processes. This paper shows that in statistical p... View full abstract»

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  • Inferring Assertion for Complementary Synthesis

    Publication Year: 2012, Page(s):1288 - 1292
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (686 KB) | HTML iconHTML

    Complementary synthesis can automatically synthesize the decoder circuit of an encoder. However, its user needs to manually specify an assertion on some configuration pins to prevent the encoder from reaching the nonworking states. To avoid this tedious task, this paper propose an automatic approach to infer this assertion, by iteratively discovering and removing cases without decoders. To discove... View full abstract»

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  • A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis

    Publication Year: 2012, Page(s):1293 - 1297
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    Process variation continues to increase with new technologies. With the advent of statistical static timing analysis (SSTA), multiple independent sources of variation can be modeled. This paper proposes a novel technique to reduce variability of metal process variation in SSTA. This novel method maximizes sensitivity cancellation to minimize variability. The developed methodology is simulated with... View full abstract»

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  • Concurrent Generation of Concurrent Programs for Post-Silicon Validation

    Publication Year: 2012, Page(s):1297 - 1302
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1865 KB) | HTML iconHTML

    The continuing trend toward increased parallelism in processor design can be seen in both the growing number of processor cores per system and in on-core hardware mechanisms that assist parallelism, such as multithreading and cache hierarchies. This complexity exacerbates the problem of ensuring the functional correctness of such hardware systems. The growing importance of post-silicon validation ... View full abstract»

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  • IEEE copyright form

    Publication Year: 2012, Page(s):1303 - 1304
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    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2012, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2012, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu