Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Issue 8 • Date Aug. 2012
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Table of contents
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information
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MARS: Matching-Driven Analog Sizing
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TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems
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FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis
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Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control
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TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC
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Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits
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A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs
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Automatic TLM Fault Localization for SystemC
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On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation
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Testability-Driven Statistical Path Selection
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Aims & Scope
Contains articles on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities.
Meet Our Editors
Editor-in-Chief
Sachin Sapatnekar
University of Minnesota
Dept. of Electrical and Computer Engineering
4-174 Keller Hall, 200 Union Street SE
Minneapolis, MN 55455 55455 USA
sachin@umn.edu
