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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 8 • Date Aug. 2012

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Displaying Results 1 - 19 of 19
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

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  • MARS: Matching-Driven Analog Sizing

    Page(s): 1145 - 1158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6956 KB) |  | HTML iconHTML  

    This paper presents a new approach for automatic computation of matching constraints for analog sizing. The method automatically analyzes a circuit netlist to generate sizing constraints. These sizing constraints are considered during a subsequent numerical optimization. It is the first method that computes symmetry constraints for sizing, based on the hierarchical structure of the circuit and a qualitative signal flow. As a unique feature, the method is capable of handling multiple signal and feedback paths, leading to multiple symmetry axes. It can be applied to linear and nonlinear circuits and any available sizing algorithm. Experimental results show that the runtime of analog sizing, as well as of result quality, are greatly improved. View full abstract»

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  • TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems

    Page(s): 1159 - 1168
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2480 KB) |  | HTML iconHTML  

    The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This urgently requires both power and thermal management during system design. In this paper, we propose a model checking-based technique using extended timed automata to solve the processor frequency assignment problem in a temperature and energy-constrained multitasking system. We also develop a polynomial time-approximation algorithm to address the state-space explosion problem caused by symbolic model checker. Our approximation scheme is guaranteed to not generate any false-positive answer, while it may return false-negative answer in rare cases. Our method is universally applicable since it is independent of any system and task characteristics. Experimental results demonstrate the usefulness of our approach. View full abstract»

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  • FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis

    Page(s): 1169 - 1179
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2330 KB) |  | HTML iconHTML  

    An efficient filter synthesis algorithm is proposed to minimize the number of adders required in the design of finite-impulse response filters. Given a specification, a filter can be synthesized by conducting two main steps: coefficient generation and multiplier-block synthesis. While most of previous works have focused on only one of the steps, the proposed algorithm integrates the two steps in an interleaved manner so as to take into account the effect of multiplier-block synthesis in generating coefficients. In addition, the concept of sensitivity is developed to reduce the complexity of computing the variable ranges of coefficients. Experimental results show that the proposed algorithm outperforms previous algorithms in terms of adder cost and takes a relatively short computation time. View full abstract»

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  • Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control

    Page(s): 1180 - 1193
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4823 KB) |  | HTML iconHTML  

    We propose an explicit numerical integration method based on matrix exponential operator for transient analysis of large-scale circuits. Solving the differential equation analytically, the limiting factor of maximum time step changes largely from the stability and Taylor truncation error to the error in computing the matrix exponential operator. We utilize Krylov subspace projection to reduce the computation complexity of matrix exponential operator. We also devise a prediction-correction scheme tailored for the matrix exponential approach to dynamically adjust the step size and the order of Krylov subspace approximation. Numerical experiments show the advantages of the proposed method compared with the implicit trapezoidal method. View full abstract»

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  • TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

    Page(s): 1194 - 1207
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (22259 KB) |  | HTML iconHTML  

    In this paper, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3-D integrated circuits (ICs). First, we analyze detailed thermomechanical stress induced by through-silicon vias in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3-D ICs. Our numerical experimental results demonstrate the effectiveness of the proposed methodology. View full abstract»

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  • An Analytical Placer for VLSI Standard Cell Placement

    Page(s): 1208 - 1221
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7512 KB) |  | HTML iconHTML  

    Placement is the process of determining the exact locations of circuit elements within a chip. It is a crucial step in very large scale integration (VLSI) physical design, because it affects routability, performance, and power consumption of a design. In this paper, we develop a new analytical placer to solve the VLSI standard cell placement problem. The placer consists of two phases, multilevel global placement (GP) and detailed cell placement (DP). In the stage of GP, during the clustering stage, we use a nonlinear programming technique and a best-choice clustering algorithm to take a global view of the whole netlist and placement information, and then use an iterative local refinement technique during the declustering stage to further distribute the cells and reduce the wirelength. In the stage of DP, we develop a fast legalization algorithm to make the solution by global placement legal and use a cell order polishing to improve the legal solution. The proposed algorithm is tested on the IBM standard cell benchmark circuits and Peko suites. Experimental results show that our placer obtains high-quality results in a reasonable running time. View full abstract»

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  • Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits

    Page(s): 1222 - 1234
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (17701 KB) |  | HTML iconHTML  

    This paper presents a design methodology for robust and low-energy clock networks for ultralow voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (Fmax) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize Fmax and minimize clock power. In addition, we implement dynamic programming (DP)-based ULV clock routing and buffering methods (deferred merging and embedding) for deterministic and statistical conditions. Experimental results show that our clock network design method achieves lower energy (more than 20% savings) at comparable or even higher Fmax compared with the existing methods. View full abstract»

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  • A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs

    Page(s): 1235 - 1248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8784 KB) |  | HTML iconHTML  

    The rapid scaling of silicon technology has enabled massive transistor integration densities. Nanometer feature sizes, however, are marred by increasing variability and susceptibility to wear-out. Billion-transistor designs, such as chip multiprocessors (CMPs), are especially vulnerable to defects. CMPs rely on a network-on-chip for all their communication needs. A single link failure within this on-chip fabric can impede, halt, or even deadlock, intertile communication, which can render the entire chip multiprocessor useless. In this paper, we present a technique capable of handling very large numbers of permanent wire failures that occur in parallel links either at manufacture-time or at runtime (dynamically). As opposed to marking an entire parallel link as faulty, whenever some wires fail, the proposed methodology employs these partially-faulty links (PFLs) to continue the transfer of information-albeit at a gracefully degraded mode-in order to maintain network connectivity. Furthermore, the presented technique can designate PFLs as fully-faulty when several wires fail, by utilizing appropriate routing algorithms that bypass nonoperational links, while still maintaining load-balance in the vicinity of PFLs. The proposed scheme employs architectural support within the on-chip routers to detect link failures and enable reconfiguration at the granularity of individual wires. Hardware synthesis confirms the low-cost nature of the proposed architecture, and full-system simulations using both synthetic network traffic and real workloads demonstrate its efficacy. View full abstract»

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  • Automatic TLM Fault Localization for SystemC

    Page(s): 1249 - 1262
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3612 KB) |  | HTML iconHTML  

    To meet today's time-to-market demands, catching bugs as early as possible during the design of a system is essential. In electronic system level design where SystemC has become the de-facto standard due to transaction level modeling (TLM), many approaches for verification have been developed. They determine an error trace that demonstrates the difference between the required and the actual behavior of the system. However, the subsequent debugging process is very time-consuming, in particular due to TLM-related faults caused by complex process synchronization and concurrency. In this paper, we present an automatic fault localization approach for SystemC TLM designs. We target typical TLM faults, such as accidentally swapped blocking and nonblocking transactions, erroneous event notification, or incorrect transaction data. The approach determines parts of the design that can be changed such that the intended behavior of the design is obtained by removing the contradiction given by the error trace. Single, as well as multiple faults, is considered. Techniques based on bounded model checking are used to find the faulty parts. We demonstrate the quality of our approach by several experiments. As shown in the experiments, the fault locations are identified very fast and hence a significant acceleration for the design of SystemC TLM models is achieved. View full abstract»

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  • On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation

    Page(s): 1263 - 1274
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4676 KB) |  | HTML iconHTML  

    Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification. One effective silicon debug technique is to monitor and trace the behaviors of the circuit during its normal operation. However, due to the associated overhead, designers can only afford to trace a small number of signals in the design. Selecting which signals to trace is therefore a crucial issue for the effectiveness of this technique. This paper proposes an automated trace signal selection strategy with a new probability-based evaluation metric, which is able to dramatically enhance the visibility in post-silicon validation. Experimental results on benchmark circuits show that the proposed technique is more effective than existing solutions. View full abstract»

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  • Testability-Driven Statistical Path Selection

    Page(s): 1275 - 1287
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2655 KB) |  | HTML iconHTML  

    In the face of large-scale process variations, statistical timing methodology has advanced significantly over the last few years, and statistical path selection takes advantage of it in at-speed testing. In deterministic path selection, the separation of path selection and test generation is known to require time consuming iteration between the two processes. This paper shows that in statistical path selection, this is not only the case, but also the quality of results can be severely degraded even after the iteration. To deal with this issue, we consider testability in the first place by integrating a satisfiability (SAT) solver, and this necessitates a new statistical path selection method. We integrate the SAT solver in a novel way that leverages the conflict analysis of modern SAT solvers, which provides more than 4X speedup without special optimizations of the SAT solver for this particular application. Our proposed method is based on a generalized path criticality metric whose properties allow efficient pruning. Our experimental results show that the proposed method achieves 47% better quality of results on average, and up to 361X speedup compared to statistical path selection followed by test generation. View full abstract»

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  • Inferring Assertion for Complementary Synthesis

    Page(s): 1288 - 1292
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (686 KB) |  | HTML iconHTML  

    Complementary synthesis can automatically synthesize the decoder circuit of an encoder. However, its user needs to manually specify an assertion on some configuration pins to prevent the encoder from reaching the nonworking states. To avoid this tedious task, this paper propose an automatic approach to infer this assertion, by iteratively discovering and removing cases without decoders. To discover all decoders that may exist simultaneously under this assertion, a second algorithm based on functional dependency is proposed to decompose , the Boolean relation that uniquely determines the encoder's input, into all possible decoders. To help the user select the correct decoder, a third algorithm is proposed to infer each decoder's precondition formula, which represents those cases that lead to this decoder's existence. Experimental results on several complex encoders indicate that our algorithm can always infer assertions and generate decoders for them. Moreover, when multiple decoders exist simultaneously, the user can easily select the correct one by inspecting their precondition formulas. View full abstract»

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  • A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis

    Page(s): 1293 - 1297
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    Process variation continues to increase with new technologies. With the advent of statistical static timing analysis (SSTA), multiple independent sources of variation can be modeled. This paper proposes a novel technique to reduce variability of metal process variation in SSTA. This novel method maximizes sensitivity cancellation to minimize variability. The developed methodology is simulated with SSTA in 65-nm technology and shows a reduction in variability. View full abstract»

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  • Concurrent Generation of Concurrent Programs for Post-Silicon Validation

    Page(s): 1297 - 1302
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    The continuing trend toward increased parallelism in processor design can be seen in both the growing number of processor cores per system and in on-core hardware mechanisms that assist parallelism, such as multithreading and cache hierarchies. This complexity exacerbates the problem of ensuring the functional correctness of such hardware systems. The growing importance of post-silicon validation is leading to an emerging type of parallel application, namely, the hardware exerciser. We describe a method for exercising parallel hardware by generating pseudorandom concurrent test programs. The test generation is carried out on the tested parallel platform and thus the generator itself is also a concurrent program. We describe the challenges associated with this technology and the approach used by the Threadmill hardware exerciser, a tool developed for the post-silicon validation of the IBM POWER7 processor. View full abstract»

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  • IEEE copyright form

    Page(s): 1303 - 1304
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu