IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Publication Year: 2012, Page(s):C1 - C4
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• IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2012, Page(s): C2
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• Short Pulse Generation With On-Chip Pulse-Forming Lines

Publication Year: 2012, Page(s):1553 - 1564
Cited by:  Papers (5)
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We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- μm CMOS process with a 500- μm long PFL, post-lay... View full abstract»

• A High-Precision On-Chip Path Delay Measurement Architecture

Publication Year: 2012, Page(s):1565 - 1577
Cited by:  Papers (13)
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In this paper, we present a novel on-chip path delay measurement architecture for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed on-chip path delay measurement (OCDM) circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed OCDM circ... View full abstract»

• Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods

Publication Year: 2012, Page(s):1578 - 1589
Cited by:  Papers (8)
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Latest evaluation of the state-of-the-art iMDPL logic style has shown small information leakage compared to its predecessor version MDPL. Concurrently, new advanced power analysis attacks specifically targeting iMDPL have been proposed. Up to now, these attacks are purely theoretic and have not been applied to an implementation. We present a comprehensive analysis of iMDPL, backed by real measurem... View full abstract»

• Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

Publication Year: 2012, Page(s):1590 - 1601
Cited by:  Papers (33)
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We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low ene... View full abstract»

• Phase Distortion to Amplitude Conversion-Based Low-Cost Measurement of AM-AM and AM-PM Effects in RF Power Amplifiers

Publication Year: 2012, Page(s):1602 - 1614
Cited by:  Papers (12)
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This work develops a simple, practical yet easily realizable method for low cost measurement of phase and amplitude distortions in radio frequency power amplifiers (RF PA). Amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions are two significant distortion effects in PAs at high output power levels, causing out of band interference in the transmitted signal and bit errors in t... View full abstract»

• A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling

Publication Year: 2012, Page(s):1615 - 1620
Cited by:  Papers (9)
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This paper presents a low voltage on-chip oscillator which can compensate process, voltage, and temperature (PVT) variation in an all-digital manner. The relative reference modeling applies a pair of ring oscillators as relative references and estimates period of the internal ring oscillator. The period estimation is parameterized by a second-order polynomial. Accordingly, the oscillator compensat... View full abstract»

• Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint

Publication Year: 2012, Page(s):1621 - 1633
Cited by:  Papers (10)
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We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated with three-dimensional (3-D) integration technology. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed tes... View full abstract»

• Accurate Current Estimation for Interconnect Reliability Analysis

Publication Year: 2012, Page(s):1634 - 1644
Cited by:  Papers (14)
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An improved and efficient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Significantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily configured to work with different combin... View full abstract»

Publication Year: 2012, Page(s):1645 - 1655
Cited by:  Papers (11)
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We designed two compact in situ NBTI and oxide degradation sensors with digital outputs in 130 nm CMOS. The 308 μm2 NBTI sensor and the 150 μm2 oxide degradation sensor provide digital frequency outputs and are compatible with a cell-based design methodology without requiring analog supplies. The sensors enable high-volume data collection and monitoring of degra... View full abstract»

• A CMOS MEMS Audio Transducer Implemented by Silicon Condenser Microphone With Analog Front-End Circuits of Audio Codec

Publication Year: 2012, Page(s):1656 - 1667
Cited by:  Papers (2)
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This study proposes a CMOS MEMS audio transducer implemented by combining a silicon condenser microphone with analog front-end audio codec circuits. The proposed CMOS MEMS audio transducer is attractive because the sensor and all the circuits are robustly and compactly integrated. The overall size of the proposed device is much smaller than traditional electrets-condenser microphones (ECMs). Anoth... View full abstract»

• Scalable Packet Classification on FPGA

Publication Year: 2012, Page(s):1668 - 1680
Cited by:  Papers (39)
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Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It has become a great challenge to develop scalable solutions for next-generation packet classificatio... View full abstract»

• A 3 GHz Wideband $Sigma Delta$ Fractional-N Synthesizer With Switched-RC Sample-and-Hold PFD

Publication Year: 2012, Page(s):1681 - 1690
Cited by:  Papers (3)
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Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I ΣΔ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is ... View full abstract»

• Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders

Publication Year: 2012, Page(s):1691 - 1704
Cited by:  Papers (7)
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We embed special function units (SFUs) in homogeneous stream processors (SPs) within a graphics processing unit (GPU), to improve its performance in running modern programmable shaders, which make poor use of a single-instruction multiple-data (SIMD) architecture. We also compact instructions, so as to reduce the size of the instruction memory, and reduce area requirements by using a partial SFU i... View full abstract»

• Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration

Publication Year: 2012, Page(s):1705 - 1714
Cited by:  Papers (30)
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Today and future NAND flash memory will heavily rely on system-level fault-tolerance techniques such as error correction code (ECC) to ensure the overall system storage integrity. Since ECC demands the storage of coding redundancy and hence degrades effective cell storage efficiency, it is highly desirable to use more powerful coding solutions that can maintain the system storage reliability at le... View full abstract»

• Testing Methodology of Embedded DRAMs

Publication Year: 2012, Page(s):1715 - 1728
Cited by:  Papers (7)
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The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a h... View full abstract»

• A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments

Publication Year: 2012, Page(s):1729 - 1737
Cited by:  Papers (3)
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This paper presents a parallel and incremental solver for stochastic capacitance extraction. The random geometrical variation is described by stochastic geometrical moments, which lead to a densely augmented system equation. To efficiently extract the capacitance and solve the system equation, a parallel fast-multipole-method (FMM) is developed in the framework of stochastic geometrical moments. T... View full abstract»

• Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

Publication Year: 2012, Page(s):1738 - 1742
Cited by:  Papers (4)
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An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired or scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (F... View full abstract»

• A Low Cost Calibrated DAC for High-Resolution Video Display System

Publication Year: 2012, Page(s):1743 - 1747
Cited by:  Papers (9)
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This paper presents a digitally enhanced strategy for current-steering digital-to-analog converters (DACs) applied to video systems. The linearity error introduced by the wittingly small current sources is evaluated by an on-chip built-in self-test scheme, which comprises a shared CalDAC, a BiasDAC, and a digital controller. Two current tuning loops are involved for error detection and compensatio... View full abstract»

• IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Publication Year: 2012, Page(s): 1748
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• IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2012, Page(s): C3
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu