# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 25

Publication Year: 2012, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2012, Page(s): C2
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• ### A Highly-Integrated 3–8 GHz Ultra-Wideband RF Transmitter With Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control

Publication Year: 2012, Page(s):1357 - 1367
Cited by:  Papers (5)
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This paper presents a highly-integrated 3-8 GHz ultra-wideband (UWB) RF transmitter implemented in a 1.2 V 0.13m CMOS technology. The transmitter integrates an analog baseband (PGAs and filter), an IQ modulator, a variable gain amplifier (VGA), a differential-to-single-ended amplifier, a power amplifier, as well as a transmitted signal strength indicator (TSSI). The RF VGA and the TSSI cooperate t... View full abstract»

• ### A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration

Publication Year: 2012, Page(s):1368 - 1372
Cited by:  Papers (4)
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A first-order time-based ΔΣ modulator using voltage-controlled oscillator (VCO) is presented. The proposed modulator employs phase interpolation technique to enhance the time resolution of the VCO and digital calibration to improve the linearity of the VCO tuning curve. The proposed modulator, implemented in 0.13 μm CMOS process, achieves 55 dB peak signal-to-noise ratio and 5... View full abstract»

• ### Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier

Publication Year: 2012, Page(s):1373 - 1382
Cited by:  Papers (3)
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This paper presents the random jitter and deterministic jitter analysis on the proposed polyphase filter (PPF)-based multiphase clock in frequency multiplier with reference to the benchmark jitter analysis of the multiphase clock counterpart using conventional delay-locked loop (DLL) approach. The analysis results have shown that the jitter performance of PPF-based design is better than that of DL... View full abstract»

• ### Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis

Publication Year: 2012, Page(s):1383 - 1391
Cited by:  Papers (5)
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The most challenging problem in the current block-based statistical static timing analysis (SSTA) is how to handle the max operation efficiently and accurately. Existing SSTA techniques suffer from limited modeling capability by using a linear delay model with Gaussian distribution, or have scalability problems due to expensive operations involved to handle non-Gaussian variation sources or nonlin... View full abstract»

• ### Exploiting Process Variability in Voltage/Frequency Control

Publication Year: 2012, Page(s):1392 - 1404
Cited by:  Papers (21)
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Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. Although manufacturing process variations are giving rise to significant core-to-core variations in power and performance, traditional DVFS controllers are unaware of these variations. Exploiting the different power profiles of the cores can sign... View full abstract»

• ### Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements

Publication Year: 2012, Page(s):1405 - 1418
Cited by:  Papers (18)  |  Patents (2)
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With technology scaling, the deviation between predicted path delay using simulation and actual path delay on silicon increases due to process variation and aging. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive measurement devices. In this paper, a novel path-delay measurement architecture called path-ba... View full abstract»

• ### Resource-Efficient FPGA Architecture and Implementation of Hough Transform

Publication Year: 2012, Page(s):1419 - 1428
Cited by:  Papers (15)
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Hough transform is widely used for detecting straight lines in an image, but it involves huge computations. For embedded application, field-programmable gate arrays are one of the most used hardware accelerators to achieve real-time implementation of Hough transform. In this paper, we present a resource-efficient architecture and implementation of Hough transform on an FPGA. The incrementing prope... View full abstract»

• ### Portable, Flexible, and Scalable Soft Vector Processors

Publication Year: 2012, Page(s):1429 - 1442
Cited by:  Papers (14)
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Field-programmable gate arrays (FPGAs) are increasingly used to implement embedded digital systems, however, the hardware design necessary to do so is time-consuming and tedious. The amount of hardware design can be reduced by employing a microprocessor for less-critical computation in the system. Often this microprocessor is implemented using the FPGA reprogrammable fabric as a soft processor whi... View full abstract»

• ### Ground Switching Load Modulation With Ground Isolation for Passive HF RFID Transponders

Publication Year: 2012, Page(s):1443 - 1452
Cited by:  Papers (2)
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This paper presents a ground switching load modulation scheme for passive HF RFID transponders. The proposed modulation scheme allows HF transponders to communicate with the reader in the strong field with a higher modulation index using simple RF clamps, compared with conventional resistive and capacitive load modulation schemes. Also presented is a ground-isolated voltage doubler rectifier to el... View full abstract»

• ### Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis

Publication Year: 2012, Page(s):1453 - 1466
Cited by:  Papers (21)
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Efficient implementation of point multiplication is crucial for elliptic curve cryptographic systems. This paper presents the implementation results of an elliptic curve crypto-processor over binary fields GF(2m) on binary Edwards and generalized Hessian curves using Gaussian normal basis (GNB). We demonstrate how parallelization in higher levels can be performed by full resource utiliz... View full abstract»

• ### Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks

Publication Year: 2012, Page(s):1467 - 1472
Cited by:  Papers (9)
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In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given delay constraint is presented. This technique takes advantage of the unique feature of four-terminal FinFETs allowing different transistors to have separately tunable back bias voltages. In this work, a reverse back bias voltage is applied to one of the two stacked transistors to reduce its leakage... View full abstract»

• ### Harvesting-Aware Power Management for Real-Time Systems With Renewable Energy

Publication Year: 2012, Page(s):1473 - 1486
Cited by:  Papers (29)
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In this paper, we propose a harvesting-aware power management algorithm that targets at achieving good energy efficiency and system performance in energy harvesting real-time systems. The proposed algorithm utilizes static and adaptive scheduling techniques combined with dynamic voltage and frequency selection to achieve good system performance under timing and energy constraints. In our approach,... View full abstract»

• ### Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

Publication Year: 2012, Page(s):1487 - 1495
Cited by:  Papers (6)
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In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high- κ/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technolo... View full abstract»

• ### UNISM: Unified Scheduling and Mapping for General Networks on Chip

Publication Year: 2012, Page(s):1496 - 1509
Cited by:  Papers (22)
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Task scheduling and core mapping have a significant impact on the overall performance of network on chip (NOC). In this paper, a unified task scheduling and core mapping algorithm called UNISM is proposed for different NOC architectures including regular mesh, irregular mesh and custom networks. First, a unified model combining scheduling and mapping is introduced using mixed integer linear progra... View full abstract»

• ### LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors

Publication Year: 2012, Page(s):1510 - 1523
Cited by:  Papers (4)
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High-end embedded processors demand complex on-chip cache hierarchies satisfying several contradicting design requirements such as high-performance operation and low energy consumption. This paper introduces light-power (LP) nonuniform cache architecture (NUCA), a tiled-cache addressing both goals. LP-NUCA places a group of small and low-latency tiles between the L1 and the last level cache (LLC) ... View full abstract»

• ### A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications

Publication Year: 2012, Page(s):1524 - 1528
Cited by:  Papers (12)
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This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been ... View full abstract»

• ### ZeROA: Zero Clock Skew Rotary Oscillatory Array

Publication Year: 2012, Page(s):1528 - 1532
Cited by:  Papers (2)  |  Patents (1)
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Resonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate. It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation. In this paper, the feasibility of zero clock skew synchronization with the rotary clocking technology implemented on t... View full abstract»

• ### Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations

Publication Year: 2012, Page(s):1532 - 1536
Cited by:  Papers (5)
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Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 8... View full abstract»

• ### A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 $times$ 4 64-QAM System

Publication Year: 2012, Page(s):1537 - 1541
Cited by:  Papers (14)
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This paper presents the algorithm and VLSI architecture of a configurable tree-searching approach that combines the features of classical depth-first and breadth-first methods. Based on this approach, techniques to reduce complexity while providing both hard and soft outputs decoding are presented. Furthermore, a single programmable parameter allows the user to tradeoff throughput versus BER perfo... View full abstract»

• ### Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection

Publication Year: 2012, Page(s):1542 - 1546
Cited by:  Papers (12)
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This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations. A ... View full abstract»

• ### Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

Publication Year: 2012, Page(s):1547 - 1551
Cited by:  Papers (13)
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In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics ... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Publication Year: 2012, Page(s): 1552
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2012, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu