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Computer Architecture Letters

Issue 1 • Date Jan.-June 2012

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Displaying Results 1 - 14 of 14
  • [Front cover and table of contents]

    Publication Year: 2012 , Page(s): c1
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  • [Cover2]

    Publication Year: 2012 , Page(s): c2
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  • A Case for Hybrid Discrete-Continuous Architectures

    Publication Year: 2012 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (106 KB) |  | HTML iconHTML  

    Current technology trends indicate that power- and energy efficiency will limit chip throughput in the future. Current solutions to these problems, either in the way of programmable or fixed-function digital accelerators will soon reach their limits as microarchitectural overheads are successively trimmed. A significant departure from current computing methods is required to carry forward computin... View full abstract»

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  • Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs

    Publication Year: 2012 , Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    State of the art fabrication technology for integrating numerous hardware resources such as Processors/DSPs and memory arrays into a single chip enables the emergence of Multiprocessor System-on-Chip (MPSoC). Stream programming paradigm based on MPSoC is highly efficient for single functionality scenario due to its dedicated and predictable data supply system. However, when memory traffic is heavi... View full abstract»

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  • A HW/SW Co-designed Programmable Functional Unit

    Publication Year: 2012 , Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor. Code is transformed and instructions are generated that run on the PFU using a co-designed virtual machine (Cd-VM). Results presented in this paper show that this HW/SW co-designed approach produces average speedups in performance of 29% i... View full abstract»

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  • A High-Level Power Model for MPSoC on FPGA

    Publication Year: 2012 , Page(s): 13 - 16
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (267 KB) |  | HTML iconHTML  

    This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the technique highly useful in the context of early system-level design space exploration. We have integrat... View full abstract»

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  • An Overview of Static Pipelining

    Publication Year: 2012 , Page(s): 17 - 20
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (145 KB) |  | HTML iconHTML  

    A new generation of mobile applications requires reduced energy consumption without sacrificing execution performance. In this paper, we propose to respond to these conflicting demands with an innovative statically pipelined processor supported by an optimizing compiler. The central idea of the approach is that the control during each cycle for each portion of the processor is explicitly represent... View full abstract»

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  • Cache Impacts of Datatype Acceleration

    Publication Year: 2012 , Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (101 KB) |  | HTML iconHTML  

    Hardware acceleration is a widely accepted solution for performance and energy efficient computation because it removes unnecessary hardware for general computation while delivering exceptional performance via specialized control paths and execution units. The spectrum of accelerators available today ranges from coarse-grain off-load engines such as GPUs to fine-grain instruction set extensions su... View full abstract»

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  • 2011 Reviewers List

    Publication Year: 2012 , Page(s): 25 - 26
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    Publication Year: 2012 , Page(s): 26
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    Publication Year: 2012 , Page(s): 28
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  • 2011 Annual Index

    Publication Year: 2012
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  • [Cover3]

    Publication Year: 2012 , Page(s): c3
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  • IEEE Computer Society [Back cover]

    Publication Year: 2012 , Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
José Martinez
Cornell University
336 Frank H.T. Rhodes Hall
Ithaca, NY 14853 USA
e-mail: martinez@cornell.edu