Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on

Issue 2 • Date June 2012

Filter Results

Displaying Results 1 - 25 of 25
  • Table of contents

    Publication Year: 2012 , Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (169 KB)  
    Freely Available from IEEE
  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems publication information

    Publication Year: 2012 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (129 KB)  
    Freely Available from IEEE
  • Guest Editorial New Interconnect Technologies in On-Chip Communication

    Publication Year: 2012 , Page(s): 121 - 123
    Save to Project icon | Request Permissions | PDF file iconPDF (549 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Exploiting New Interconnect Technologies in On-Chip Communication

    Publication Year: 2012 , Page(s): 124 - 136
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1027 KB) |  | HTML iconHTML  

    The continuing scaling of transistors has increased the number of cores available in current processors, and the number of cores is expected to continue to increase. In such many core processors, the communication between cores with the on-chip interconnect is becoming a challenge as it not only must provide low latency and high bandwidth but also needs to be cost-effective in terms of power consumption. The communication challenge is not only within a single chip but providing high bandwidth to the increasing number of cores from off-chip memory is also a challenge. The conventional metal interconnect is limited, especially for global communication, and can not scale efficiently. In this paper, we investigate alternative interconnect technologies that can be exploited to address the communication challenges in future many core processor. We provide an overview of the different technologies that are available and then, investigate how these interconnect technologies impact the architecture of the on-chip communication and the system design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Designing Chip-Level Nanophotonic Interconnection Networks

    Publication Year: 2012 , Page(s): 137 - 153
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2067 KB) |  | HTML iconHTML  

    Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-efficiency compared to electrical networks. This paper discusses the approach we have used when designing such networks, and provides a foundation for designing new networks. We begin by briefly reviewing the basic silicon-photonic device technology before outlining design issues and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural level, and the physical level. In designing our own networks, we use an iterative process that moves between these three levels of design to meet application requirements given our technology constraints. We use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures

    Publication Year: 2012 , Page(s): 154 - 168
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2070 KB) |  | HTML iconHTML  

    Nanophotonic architectures have recently been proposed as a path to providing low latency, high bandwidth network-on-chips. These proposals have primarily been based on micro-ring resonator modulators which, while capable of operating at tremendous speed, are known to have both a high manufacturing induced variability and a high degree of temperature dependence. The most common solution to these two problems is to introduce small heaters to control the temperature of the ring directly, which can significantly reduce overall power efficiency. In this paper, we introduce plasmonics as a complementary technology. While plasmonic devices have several important advantages, they come with their own new set of restrictions, including propagation loss and lack of wave division multiplexing (WDM) support. To overcome these challenges we propose a new hybrid photonic/plasmonic channel that can support WDM through the use of photonic micro-ring resonators as variation tolerant passive filters. Our aim is to exploit the best of both technologies: wave-guiding of photonics, and modulating using plasmonics. This channel provides moderate bandwidth with distance independent power consumption and a higher degree of temperature and process variation tolerance. We describe the state of plasmonics research, present architecturally-useful models of many of the most important devices, explore new ways in which the limitations of the technology can most readily be minimized, and quantify the applicability of these novel hybrid schemes across a variety of interconnect strategies. Our link-level analysis shows that the hybrid channel can save from 28% to 45% of total channel energy-cost per bit depending on process variation conditions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DCOF—An Arbitration Free Directly Connected Optical Fabric

    Publication Year: 2012 , Page(s): 169 - 182
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1547 KB) |  | HTML iconHTML  

    In this paper, we investigate the unique potential of optics to provide a family of arbitration free topologies that are not realizable using conventional electronics. This is accomplished by creating a directly connected fabric of waveguides that can be configured to support everything from a crossbar to fully connected topologies. The large number of waveguides required to create a directly connected optical fabric (DCOF) can be built by taking advantage of multiple photonic layers connected with photonic vias, allowing the architect to choose the degree of simultaneous communication (a parameter called) necessary to meet the performance requirements and available power budget. In order to evaluate DCOF we developed a detailed implementation model for three different network instantiations-a crossbar similar to Corona, DCOF configured as a crossbar, and DCOF configured as a fully connected network. We analyzed the power consumption and performance of these topologies on a variety of benchmarks, including SPLASH-2 and synthetic traces. Our results demonstrate that the overhead required by arbitration is nontrivial, especially at high loads. Eliminating the need for arbitration, sizing the buffers carefully and retransmitting lost packets when there is contention results in a significant reduction in average packet latency without additional power overhead. We also show that when configured as a crossbar DCOF is the most energy efficient while maintaining excellent performance, and when configured as a fully connected network provides the best performance, but at a potentially prohibitive photonic power cost. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Using Transmission Lines for Global On-Chip Communication

    Publication Year: 2012 , Page(s): 183 - 193
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1422 KB) |  | HTML iconHTML  

    The growing number of cores in chip multiprocessors increases the importance of interconnection for overall system performance and energy efficiency. Compared to traditional distributed shared-memory architectures, chip-multiprocessors (CMPs) offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. Worsening wire delays, energy-inefficient routers, and the decreased importance of in-field scalability, make the conventional packet-switched network-on-chip a less attractive option. An alternative solution uses well-engineered transmission lines as communication links. These transmission lines, along with simple, practical circuits using modern complementary metal-oxide-semiconductor technology, can provide low latency, low energy, high throughput channels which can be used as a shared-medium point-to-point link. The design of the transmission lines and transceiver circuits has important architectural impact. This paper includes a first-step design effort for these components, particularly when used for a globally shared-medium bus. For medium-scale CMPs, this interconnect backbone can eliminate the need for packet switching and provide energy, as well as performance benefits when compared to a conventional mesh interconnect. We will provide a design of such a system from the ground up, including design of the transmission lines, transceiver circuits, and a simple, yet effective, architectural design for a shared-medium interconnect, and show that such a design can be a compelling alternative to packet-switched networks for CMPs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Millimeter-Wave Transmission Line in 90-nm CMOS Technology

    Publication Year: 2012 , Page(s): 194 - 199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1260 KB) |  | HTML iconHTML  

    A twice interleaved metal patterns is proposed for decreasing transmission line loss and maintaining operating bandwidth when using 90-nm complementary metal-oxide-semiconductor technology. Three transmission lines are implemented in this experiment. The measurement results show that the location of interleaved metal patterns in metal-1 and metal-2 films decreases the attenuation constant and increases the operating bandwidth compared to the conventional transmission line. To deeply understand the phenomenon, the effective height is calculated to analyze the experiment result. The comparison results show the proposed and conventional transmission lines obtain attenuation constants of 0.26 dB/mm and 0.71 dB/mm at 40 GHz . The proposed transmission line can potentially make huge improvements in millimeter-wave operation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface

    Publication Year: 2012 , Page(s): 200 - 209
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2897 KB) |  | HTML iconHTML  

    A noncoherent amplitude shift keying (ASK)-based RF-interconnect (RF-I) system design for off-chip communication is analyzed. The proposed RF-I system exploits the simple architecture and characteristics of noncoherent ASK modulation. This provides an efficient way of increasing interconnect bandwidth by transmitting an RF-modulated data stream simultaneously with a conventional baseband counterpart over a shared off-chip transmission line. Both analysis and tested results prove that the performance of the proposed dual-band (RF+baseband) interconnect system is not limited by thermal noise interference. Therefore, a more sophisticated modulation scheme and/or coherent receiving scheme becomes unnecessary within the scope of system requirements. In addition, it confirms that the proposed inductive coupling network is able to support simultaneous bidirectional communications without using complicated replica circuits or additional filters to isolate simultaneous baseband and RF-band data streams. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

    Publication Year: 2012 , Page(s): 210 - 227
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2589 KB) |  | HTML iconHTML  

    The demand for capacity and off-chip bandwidth to dynamic random-access memory (DRAM) will continue to grow as we integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of dual in-line memory modules (DIMMs) supported on a multi-drop bus has decreased. Therefore, traditional memory systems are not sufficient to meet both these demands. We propose the DIMM tree architecture for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is able to grow the number of DIMMs exponentially with each level of latency in the tree. We also propose application of multiband radio-frequency interconnect (MRF-I) to the DIMM tree architecture for even greater scalability and higher throughput. The DIMM tree architecture without MRF-I was able to scale up to 64 DIMMs with only an 8% degradation in throughput over an ideal system. The DIMM tree architecture with MRF-I was able to increase throughput by 68% (up to 200%) on a 64-DIMM system over a 4-DIMM system. Finally, we propose the partitioned DIMM tree, which allows the scaling of a main memory system to a many-DIMM memory system while still maintaining high throughput. The partitioned DIMM tree is able to improve throughput by an average of 19% up to 35% over the DIMM tree with 256 DIMMs on a single channel. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

    Publication Year: 2012 , Page(s): 228 - 239
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1261 KB) |  | HTML iconHTML  

    Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices

    Publication Year: 2012 , Page(s): 240 - 248
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1486 KB) |  | HTML iconHTML  

    Through-silicon vias (TSVs) have two negative effects in the design of three-dimensional integrated circuits (3-D ICs). First, TSV insertion leads to silicon area overhead. In addition, nonnegligible TSV capacitance causes delay overhead in 3-D signal paths. Therefore, obtaining all benefits such as wirelength reduction and performance improvement from 3-D ICs is highly dependent on TSV size and capacitance. Meanwhile, TSVs are downscaled to minimize their negative effects, and sub-micron TSVs are expected to be fabricated in the near future. At the same time, the devices are also downscaled beyond 32 nm and 22 nm, so future 3-D ICs will very likely be built with sub-micron TSVs and advanced device technologies. In this paper, we investigate the impact of sub-micron TSVs on the quality of today and future 3-D ICs. For future process technologies, we develop 22 nm and 16 nm libraries. Using these future process libraries and an existing 45 nm library, we generate 3-D IC layouts with different TSV sizes and capacitances and study the impact of sub-micron TSVs thoroughly. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1 TB/s 1 pJ/b 6.4 {\rm mm}^{2}/{\rm TB/s} QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

    Publication Year: 2012 , Page(s): 249 - 256
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1644 KB) |  | HTML iconHTML  

    1 TB/s 1 pJ/b 6.4 mm2 /TB/s QDR inductive-coupling interface between 65-nm complementary metal-oxide-semicon ductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <;10-10 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Simultaneous Bi-Directional Transceivers Utilizing Capacitive Coupling for 3DICs in Face-to-Face Configuration

    Publication Year: 2012 , Page(s): 257 - 265
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1551 KB) |  | HTML iconHTML  

    Capacitive-coupling-based simultaneously bi-directional transceivers for chip-to-chip communication in three-dimensional integrated circuits are presented. By employing a 4-level signaling strategy with a novel cascaded capacitor configuration, the proposed transceivers can transmit and receive data simultaneously through a single inter-chip coupling capacitor, and effectively improve the throughput per interconnect. In this work, the proposed cascaded capacitor structure and its signaling strategy are discussed in details and circuit solutions for transceivers are presented. A parasitic shielding technique is employed in the electrode design to improve signal swings without area overheads. A 16μm×20μm electrode provides the voltage margin as large as 195 mV at 1.2 V supply (verified by post-layout simulation) for signal sensing and recovery. The proposed transceivers are designed in a commercial 65-nm complementary metal-oxide-semiconductor technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

    Publication Year: 2012 , Page(s): 266 - 277
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1869 KB) |  | HTML iconHTML  

    In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that are not possible in complementary metal-oxide-semiconductor-based homogeneous 3-D NoCs. We demonstrate that the proposed 3-D hybrid architecture shows significant improvements in all network parameters including latency, power, and energy consumption compared to other practical 3-D NoCs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Swizzle-Switch Networks for Many-Core Systems

    Publication Year: 2012 , Page(s): 278 - 294
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3384 KB) |  | HTML iconHTML  

    This work revisits the design of crossbar and high-radix interconnects in light of advances in circuit and layout techniques that improve crossbar scalability, obviating the need for deep multi-stage networks. We employ a new building block, the Swizzle-Switch-an energy and area-efficient switching element that can readily scale to radix 64-that has recently been validated via silicon test chips in 45 nm technology. We evaluate the Swizzle-Switch as both the high-radix building block of a Flattened Butterfly and as a single-stage interconnect, the Swizzle-Switch Network. In the process we address the architectural and layout challenges associated with centralized crossbar systems. Compared to a conventional Mesh, the Flattened Butterfly provides a 15% performance improvement with a 2.5× reduction in the standard deviation of on-chip access times. The Swizzle-Switch Network achieves further gains, providing a 21% improvement in performance, a 3× reduction in on-chip access variability, a 33% reduction in interconnect power, and a 25% reduction in total system energy while only increasing chip area by 7%. Finally, this paper details a 3-D integrated version of the Swizzle-Switch Network, showing up to a 30% gain in performance over the 2-D Swizzle-Switch Network for benchmarks sensitive to interconnect latency. One major concern with 3-D designs is thermal dissipation. We show through detailed thermal analysis that with the highly energy-efficient Swizzle-Switch Network design that the thermal budget is well within that of passive cooling solutions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

    Publication Year: 2012 , Page(s): 295 - 306
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2613 KB) |  | HTML iconHTML  

    An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3-D network-on-chip (NoC), which can route packets in the vertical direction. Superimposing identical planar dies minimizes design effort and manufacturing costs, ensuring at the same time high flexibility and reconfigurability. A single die can be used either as a fully testable standalone chip multi-processor (CMP), or integrated in a 3-D stack, increasing the overall core count and consequently the system performance. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90 nm complementary metal-oxide-semiconductor process and stacked using an in-house, via-last Cu-TSV process. Initial results show that the proposed 3-D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gb/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers

    Publication Year: 2012 , Page(s): 307 - 313
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1849 KB) |  | HTML iconHTML  

    This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS

    Publication Year: 2012 , Page(s): 314 - 321
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2068 KB) |  | HTML iconHTML  

    In this paper, a high-frequency crosstalk compensation scheme for high speed multi-channel on-chip interconnect is proposed. In the proposed scheme, a zero is inserted to the aggressor branch of the crosstalk feed-forward equalizer, which compensates for the high-frequency crosstalk, resulting in reduced timing jitter and increased eye opening. In order to verify the proposed scheme, an eight-channel 10-mm on-chip interconnect is implemented in 130-nm CMOS process. Measurement results show that the proposed scheme effectively removes the high frequency crosstalk and achieves a data rate of 2.9 Gb/s at a bit-error-rate below . The power consumption of the proposed transceiver is about 1 mW which corresponds to an energy efficiency of 0.4 pJ/bit. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach

    Publication Year: 2012 , Page(s): 322 - 332
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2197 KB) |  | HTML iconHTML  

    Wire shaping for delay/power minimization has been extensively studied. Due to the perceived high design and manufacturing costs for using nonregular wire shapes, wire shaping is generally considered to be impractical. In this paper, we present a practical wire shaping method to reduce power consumption of interconnect. Nonregular wire shapes are directly implemented on silicon wafer instead of in GDSII during design. We present novel enhancements to existing optical proximity correction (OPC) technology to accurately print nonregular wire shapes. Experimental results show that the post-OPC mask complexities of uniform wire and nonregular wire are comparable. With minimal impact on the design and manufacturing flows and minimal additional design and manufacturing costs, we demonstrate that wire shaping can help to obtain substantial reduction of interconnect dynamic power without affecting timing closure. Our wire shaping methodology is an excellent example of Manufacturing for Design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors

    Publication Year: 2012 , Page(s): 333
    Save to Project icon | Request Permissions | PDF file iconPDF (37 KB)  
    Freely Available from IEEE
  • IEEE Xplore Digital Library [advertisement]

    Publication Year: 2012 , Page(s): 334
    Save to Project icon | Request Permissions | PDF file iconPDF (1347 KB)  
    Freely Available from IEEE
  • IEEE Copyright Form

    Publication Year: 2012 , Page(s): 335 - 336
    Save to Project icon | Request Permissions | PDF file iconPDF (1564 KB)  
    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Publication Year: 2012 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (32 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Journal on Emerging and Selected Topics in Circuits and Systems publishes special issues covering the entire Field of Interest of the IEEE Circuits and Systems Society and with particular focus on emerging areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Manuel Delgado-Restituto
Instituto Nacional de Microelectrónica de Sevilla
IMSE-CNM (CSIC/Universidad de Sevilla)