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# IEEE Transactions on Device and Materials Reliability

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Displaying Results 1 - 25 of 53
• ### [Front cover]

Publication Year: 2012, Page(s): C1
| PDF (226 KB)
• ### IEEE Transactions on Device and Materials Reliability publication information

Publication Year: 2012, Page(s): C2
| PDF (128 KB)

Publication Year: 2012, Page(s):185 - 187
| PDF (57 KB)
• ### Forward to the Special Section on “Materials, Processing, and Reliability of 3-D Interconnects”

Publication Year: 2012, Page(s): 188
| PDF (23 KB) | HTML
• ### Design and Fabrication of a Silicon Interposer With TSVs in Cavities for Three-Dimensional IC Packaging

Publication Year: 2012, Page(s):189 - 193
Cited by:  Papers (4)
| | PDF (462 KB) | HTML

Flip chip is one of the packaging techniques for high-performance components. There is a greater demand on integrating more functions in a smaller chip nowadays. This leads to the increase of I/O density. Organic substrate is the bottleneck of the high-density packaging. A silicon interposer with through-silicon vias (TSVs) is commonly used to provide a platform with a high wiring density to redis... View full abstract»

• ### Three-Dimensional Wafer Stacking Using Cu–Cu Bonding for Simultaneous Formation of Electrical, Mechanical, and Hermetic Bonds

Publication Year: 2012, Page(s):194 - 200
Cited by:  Papers (22)  |  Patents (1)
| | PDF (845 KB) | HTML

Wafer-on-wafer stacking is demonstrated successfully using bumpless Cu-Cu bonding for the simultaneous formation of electrical connection, mechanical support, and hermetic frame for 3-D IC application. The ohmic behavior of the Cu-Cu bond is verified. A daisy chain of at least 44 000 contacts at a 15-μm pitch is connected successfully and sustains thermal cycling. Postbonding delamination i... View full abstract»

• ### Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package With Through-Silicon Via

Publication Year: 2012, Page(s):201 - 208
Cited by:  Papers (12)
| | PDF (1352 KB) | HTML

In this paper, the reliability of a pyramidal-shape three-die-stacked package with through-silicon via (TSV) is studied experimentally and numerically. The initially designed microbumps are located peripherally along the edge of the TSV die, which induces a concentrated bending force on the lower die when the upper die is stacked. Finite-element (FE) simulation results show that such bump layout i... View full abstract»

• ### A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Publication Year: 2012, Page(s):209 - 216
Cited by:  Papers (9)
| | PDF (1228 KB) | HTML

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In ad... View full abstract»

• ### A Critical Review on Multiscale Material Database Requirement for Accurate Three-Dimensional IC Simulation Input

Publication Year: 2012, Page(s):217 - 224
Cited by:  Papers (2)
| | PDF (650 KB) | HTML

Material behavior and properties at different scales, from nanometers to millimeters, are the input data needed for a model-based design-for-manufacturing approach of 3-D through-silicon-via (TSV) stacked ICs. In particular, mechanical and thermomechanical material data have to be used as input for physics-based modeling and simulation of stress-induced phenomena in 3-D stacks. Both package- and w... View full abstract»

• ### Copper Anisotropy Effects in Three-Dimensional Integrated Circuits Using Through-Silicon Vias

Publication Year: 2012, Page(s):225 - 232
Cited by:  Papers (7)
| | PDF (1019 KB) | HTML

The elastic anisotropy of copper through-silicon vias (TSVs) and its impact on performance and reliability in 3-D integrated structures is examined. Copper TSVs exhibit significant amount of elastic anisotropy, particularly for TSVs with very small diameters. The elastic anisotropy manifests itself in terms of different Young's moduli in different directions and results in orientation-dependent st... View full abstract»

• ### Critical Concerns in Soldering Reactions Arising from Space Confinement in 3-D IC Packages

Publication Year: 2012, Page(s):233 - 240
Cited by:  Papers (41)
| | PDF (749 KB) | HTML

Six critical issues relating to interfacial reactions arising from space confinement in 3-D integrated-circuit (3-D IC) packaging are presented in this paper. The first issue arises from the concern that intermetallics (IMCs) may occupy a large portion of the solder joint volume. It will be demonstrated that this concern is real even for Ni under bump metallurgy (UBM) or surface finish, which reac... View full abstract»

• ### Simulations of Damage, Crack Initiation, and Propagation in Interlayer Dielectric Structures: Understanding Assembly-Induced Fracture in Dies

Publication Year: 2012, Page(s):241 - 254
Cited by:  Papers (11)  |  Patents (1)
| | PDF (1341 KB) | HTML

Performance enhancement by lowering the dielectric constant of interlayer dielectric (ILD) materials often compromises the mechanical integrity of the dielectric stack. At the present time, fracture in the ILD stacks induced by assembly to either an organic substrate or a die stack (3-D) is an important reliability consideration. These interactions include what is popularly referred to as the chip... View full abstract»

• ### Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration

Publication Year: 2012, Page(s):255 - 262
Cited by:  Papers (65)
| | PDF (782 KB) | HTML

Three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in the TSV structures can affect the device performance by degrading carrier mobility and raise serious reliability concerns. In this paper, the effect of thermal stresses in TSV structure... View full abstract»

• ### Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

Publication Year: 2012, Page(s):263 - 271
Cited by:  Papers (20)
| | PDF (1236 KB) | HTML

A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and... View full abstract»

• ### Physics-Based Models for EM and SM Simulation in Three-Dimensional IC Structures

Publication Year: 2012, Page(s):272 - 284
Cited by:  Papers (8)
| | PDF (1567 KB) | HTML

Relaxation of stress generated inside through-silicon via (TSV), in regions of interconnect and regions of silicon adjusted to TSV by microstructure evolution during high-temperature anneal and by wafer/die cooling down to test/operation conditions, is critical for establishing a final equilibrium state. A model for stress relaxation governed by vacancy generation and migration is developed. The c... View full abstract»

• ### Through Silicon Via Reliability

Publication Year: 2012, Page(s):285 - 295
Cited by:  Papers (31)
| | PDF (1109 KB) | HTML

Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introd... View full abstract»

• ### Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking

Publication Year: 2012, Page(s):296 - 305
Cited by:  Papers (14)
| | PDF (1225 KB) | HTML

As the demands for portable electronic products increase, through-silicon-via (TSV)-based three-dimensional integrated-circuit (3-D IC) integration is becoming increasingly important. Micro-bump-bonded interconnection is one approach that has great potential to meet this requirement. In this paper, a 30-μm pitch chip-to-chip (C2C) interconnection with Cu/Ni/SnAg micro bumps was assembled us... View full abstract»

• ### Nitrided $hbox{La}_{2}hbox{O}_{3}$ as Charge-Trapping Layer for Nonvolatile Memory Applications

Publication Year: 2012, Page(s):306 - 310
Cited by:  Papers (8)
| | PDF (494 KB) | HTML

Charge-trapping characteristics of La2O3 with and without nitrogen incorporation were investigated based on Al/Al2O3/La2O3/SiO2/Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with La2<... View full abstract»

• ### A Novel Short-Channel Model for Threshold Voltage of Trigate MOSFETs With Localized Trapped Charges

Publication Year: 2012, Page(s):311 - 316
Cited by:  Papers (7)
| | PDF (618 KB) | HTML

Based on the scaling equation and perimeter-weighted-sum approach, a novel short-channel threshold voltage model for the trigate (TG) MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flatband voltage. The model shows how the positive/negative trapped charges, silicon thickness, silicon width, oxide thickness, and normalized... View full abstract»

• ### The Electrochemical Effects of Immersion Au on Electroless Nickel and Its Consequences on the Hermetic Reliability of a Semiconductor Device

Publication Year: 2012, Page(s):317 - 322
| | PDF (633 KB) | HTML

We have analyzed the effects of the thicknesses of immersion Au (i-Au) and electroless nickel (e-Ni) on the reliability of a semiconductor device that has special constraints on the absolute thicknesses of Ni and Au layers. The electrochemical reactions involved in the deposition of i-Au over Ni involve a substitution process by which Ni atoms are replaced by Au atoms. We demonstrate that, in some... View full abstract»

• ### HfSiO Bulk Trap Density Controls the Initial $V_{rm th}$ in nMOSFETs

Publication Year: 2012, Page(s):323 - 334
| | PDF (1621 KB) | HTML

The underlying physical mechanism of the Vth adjustment of nMOSFETs with HfSiO/TiN gate stack obtained by As and Ar implantation is investigated. It is experimentally proved that the trapped charge in the HfSiO bulk defects controls the initial Vth value in nMOSFETs. The reduction of the charged trap density in HfSiO by implant explains the tuned Vth... View full abstract»

• ### Error-Detection Enhanced Decoding of Difference Set Codes for Memory Applications

Publication Year: 2012, Page(s):335 - 340
Cited by:  Papers (2)
| | PDF (174 KB) | HTML

To prevent soft errors from causing data corruption, memories are typically protected with error correction codes (ECCs). For example, single-error correction (SEC) codes that can correct one error in a memory word are commonly used. More advanced ECCs are also used when additional protection is needed. While the error correction capability of a code is important, it is also important to detect er... View full abstract»

• ### Aggravated Electromigration of Copper Interconnection Lines in ULSI Devices Due to Crosstalk Noise

Publication Year: 2012, Page(s):341 - 346
Cited by:  Papers (1)
| | PDF (550 KB) | HTML

In this paper, the impact of crosstalk noise between two adjacent interconnection lines, namely, the aggressor and a victim line, upon electromigration (EM) and Joule-heating failure mechanisms in ULSI microchips has been studied. It was shown that the crosstalk noise leads to distortions of signal waveforms at the far end of the victim line, i.e., the signals supplied to the input of a far-end CM... View full abstract»

• ### Moisture-Induced Surface Corrosion in AZO Thin Films Formed by Atomic Layer Deposition

Publication Year: 2012, Page(s):347 - 356
Cited by:  Papers (12)
| | PDF (1206 KB) | HTML

Aluminum-doped zinc oxide (AZO) thin film is a viable alternative to tin-doped indium oxide, the dominant transparent conducting oxide used in solar cells. The durability of the AZO thin films grown by atomic layer deposition technique, which is known to form layers with atomic layer precision, is studied. The AZO films were subjected to the harsh environmental conditions of varying temperatures a... View full abstract»

• ### Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes Through Selective Bit Placement

Publication Year: 2012, Page(s):357 - 362
Cited by:  Papers (22)
| | PDF (183 KB) | HTML

Hamming codes that can correct one error per word are widely used to protect memories or registers from soft errors. As technology scales, radiation particles that create soft errors are more likely to affect more than 1 b when they impact a memory or electronic circuit. This effect is known as a multiple cell upset (MCU), and the registers or memory cells affected by an MCU are physically close. ... View full abstract»

## Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.