By Topic

Microwave Theory and Techniques, IEEE Transactions on

Issue 6 • Date June 2012

Filter Results

Displaying Results 1 - 25 of 31
  • Table of contents

    Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (48 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Microwave Theory and Techniques publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (45 KB)  
    Freely Available from IEEE
  • Guest Editorial

    Page(s): 1753 - 1754
    Save to Project icon | Request Permissions | PDF file iconPDF (96 KB)  
    Freely Available from IEEE
  • LDMOS Technology for RF Power Amplifiers

    Page(s): 1755 - 1763
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2689 KB) |  | HTML iconHTML  

    We show the status of laterally diffused metal-oxide-semiconductor (LDMOS) technology, which has been the device of choice for RF power applications for more than one decade. LDMOS fulfills the requirements for a wide range of class AB and pulsed applications, such as base station, broadcast, and microwave. We present state-of-the-art RF performance of the LDMOS transistor measured with a load-pull test setup, achieving class-AB drain efficiencies of 70% at 2 GHz for on-wafer and packaged devices. Furthermore, the results for several class-AB and Doherty amplifier implementations constructed with this technology are shown. As an illustration, a three-way Doherty application is demonstrated, which has a 7.5-dB back-off efficiency of 47% at 1.8 GHz with a peak power of 700 W and linearity numbers better than -65 dBc. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs

    Page(s): 1764 - 1783
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3801 KB) |  | HTML iconHTML  

    Gallium-nitride power transistor (GaN HEMT) and integrated circuit technologies have matured dramatically over the last few years, and many hundreds of thousands of devices have been manufactured and fielded in applications ranging from pulsed radars and counter-IED jammers to CATV modules and fourth-generation infrastructure base-stations. GaN HEMT devices, exhibiting high power densities coupled with high breakdown voltages, have opened up the possibilities for highly efficient power amplifiers (PAs) exploiting the principles of waveform engineered designs. This paper summarizes the unique advantages of GaN HEMTs compared to other power transistor technologies, with examples of where such features have been exploited. Since RF power densities of GaN HEMTs are many times higher than other technologies, much attention has also been given to thermal management-examples of both commercial “off-the-shelf” packaging as well as custom heat-sinks are described. The very desirable feature of having accurate large-signal models for both discrete transistors and monolithic microwave integrated circuit foundry are emphasized with a number of circuit design examples. GaN HEMT technology has been a major enabler for both very broadband high-PAs and very high-efficiency designs. This paper describes examples of broadband amplifiers, as well as several of the main areas of high-efficiency amplifier design-notably Class-D, Class-E, Class-F, and Class-J approaches, Doherty PAs, envelope-tracking techniques, and Chireix outphasing. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of CMOS Power Amplifiers

    Page(s): 1784 - 1796
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1850 KB) |  | HTML iconHTML  

    This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back-off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias-point optimization are used to increase the output power and linearity of the “analog” amplifier. In the second approach, a mixed-signal “digital” polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Controlling Active Load–Pull in a Dual-Input Inverse Load Modulated Doherty Architecture

    Page(s): 1797 - 1804
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1469 KB) |  | HTML iconHTML  

    Mathematical analysis of Doherty amplifiers have assumed many simplifications. Most notably, the peaking amplifier does not contribute power into the load and the peaking stage has an observed impedance of infinity. This paper will show that these simplifications impair the performance of a single-input Doherty amplifier and that phase tuning for compensation is needed to improve the overall system performance. The dual-input Doherty amplifier is capable of overcoming the limitations of power-dependent phase imbalance and phase compensation lines at the input of the peaking stage; however, the characterization of such an architecture is not straightforward. A new measurement technique is proposed to measure dc current, dc voltage, and output power levels to allow unique characterization of a dual-input Doherty amplifier. Phase compensation lines at the input of the peaking amplifier will be shown to be not required, as long as correct offset lines are calculated for both the carrier and peaking stage and that the λ/4 transmission-line length is not necessarily required for active load-pull. Results of a dual-input inverse load modulated Doherty amplifier are presented where the peaking stage delivers 10 dB less of maximum output power than the carrier, while still maintaining Doherty behavior. The peaking stage can therefore be implemented with a smaller device than the carrier. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 12-W X -Band MMIC HPA and Driver Amplifiers in InGaP-GaAs HBT Technology for Space SAR T/R Modules

    Page(s): 1805 - 1816
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2312 KB) |  | HTML iconHTML  

    The chip-set for the transmitting power lineup of satellite SAR antenna T/R modules has been designed and implemented exploiting a 2- μm GaInP-GaAs heterojunction bipolar transistor (HBT) technology suitable for space applications. The HBT technology features an integrated emitter ballast resistor that enables high-power density operation without suffering thermal runaway phenomena. Two monolithic microwave integrated circuit (MMIC) driver amplifiers and a MMIC HPA are described: the drivers exhibit small-signal gains exceeding 21 dB and P1 dB output power of about 28 and 29 dBm, respectively, in a 2-GHz bandwidth and CW condition. The HPA delivers more than 40-dBm power at about 2.5-dB gain compression and power-added efficiency (PAE) exceeding 36% in a 700-MHz bandwidth in pulsed operation. Its peak performance at the center of the band are 40.9-dBm output power and 45% PAE. These performance are obtained within tight de-rating conditions for space applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiharmonic Volterra Model Dedicated to the Design of Wideband and Highly Efficient GaN Power Amplifiers

    Page(s): 1817 - 1828
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3612 KB) |  | HTML iconHTML  

    This paper presents a complete validation of the new behavioral model called the multiharmonic Volterra (MHV) model for designing wideband and highly efficient power amplifiers with packaged transistors in computer-aided design (CAD) software. The proposed model topology is based on the principle of the harmonic superposition introduced by the Agilent X-parameters, which is combined with the dynamic Volterra theory to give an MHV model that can handle short-term memory effects. The MHV models of 10- and 100-W packaged GaN transistors have been extracted from time-domain load-pull measurements under continuous wave and pulsed modes, respectively. Both MHV models have been implemented into CAD software to design 10- and 85-W power amplifiers in L- and S-bands. Finally, the first power amplifier exhibited mean measured values of 10-W output power and 65% power-added efficiency over 36% bandwidth centered at 2.2 GHz, while the second one exhibited 85-W output power and 65% drain efficiency over 50% bandwidth centered at 1.6 GHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Adaptive Highly Efficient GaN Power Amplifier for Octave-Bandwidth Application and Dynamic Load Modulation

    Page(s): 1829 - 1839
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2414 KB) |  | HTML iconHTML  

    This paper presents a novel adaptive power amplifier (PA) architecture for performing dynamic-load-modulation. For the first time, a dynamically-load-modulated PA design that achieves octave bandwidth, high power and high efficiency simultaneously is experimentally demonstrated. This PA design is based on a commercial GaN HEMT. The output matching scheme incorporates a broadband static matching for high-efficiency at the maximum power level and a wideband dynamic matching for efficiency enhancement at power back-offs. The impedance and frequency tunability is realized using silicon diode varactors with a very high breakdown voltage of 90 V. Experimental results show that a dynamic-load-modulation from maximum power to 10-dB back-off is achieved from 1 to 1.9 GHz, with a measured performance of ≈10-W peak power, ≈10-dB gain, 64%-79% peak-power efficiency, and 30%-45% efficiency at 10-dB power back-off throughout this band. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a Concurrent Dual-Band 1.8–2.4-GHz GaN-HEMT Doherty Power Amplifier

    Page(s): 1840 - 1849
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1957 KB)  

    In this paper, the design, implementation, and experimental results of a high-efficiency dual-band GaN-HEMT Doherty power amplifier (DPA) are presented. An extensive discussion about the design of the passive structures is presented showing different possible topologies of the dual-band DPA. One of the proposed topologies is used to design a dual-band DPA in hybrid technology for the frequency bands 1.8 and 2.4 GHz with the second efficiency peak at 6-dB output power back-off (OBO). For a continuous-wave output power of 20 W, the measured power-added efficiency (PAE) is 64% and 54% at 1.8 and 2.4 GHz, respectively. At -dB OBO, the resulting measured PAEs were 60% and 44% in the two frequency bands. Linearized concurrent modulated measurement using 10-MHz LTE signal with 7-dB peak-to-average-ratio (PAR) at 1.8 GHz and 10-MHz WiMAX signal with 8.5-dB PAR at 2.4 GHz shows an average PAE of 34%, at an adjacent channel leakage ratio of -48 dBc and -46 dBc at 1.8 and 2.4 GHz, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a Wideband High-Voltage High-Efficiency BiCMOS Envelope Amplifier for Micro-Base-Station RF Power Amplifiers

    Page(s): 1850 - 1861
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2522 KB) |  | HTML iconHTML  

    A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage (VDD = 15 V) envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A WCDMA envelope-tracking RF PA at 2.14 GHz, including a GaN field-effect transistor RF stage, has an overall drain efficiency above 51%, with a normalized power root-mean-square error below 1.2% and an adjacent channel leakage ratio of -49 dBc at 5-MHz offset using memory-effect mitigation digital pre-distortion, at an average output power above 2 W and a gain of 10 dB. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-Efficiency Cellular Power Amplifiers Based on a Modified LDMOS Process on Bulk Silicon and Silicon-On-Insulator Substrates With Integrated Power Management Circuitry

    Page(s): 1862 - 1869
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1638 KB) |  | HTML iconHTML  

    An RF high-voltage CMOS technology is presented for cost-effective monolithic integration of cellular RF transmit functions. The technology integrates a modified LDMOS RF power transistor capable of nearly comparable linear and saturated RF power characteristics to GaAs solutions at cellular frequency bands. Measured results for multistage cellular power amplifier (PA) designs processed on bulk-Si and silicon-on-insulator on high-resistivity Si substrates (1 kΩ·cm ) are presented. The low-band multistage PA achieves greater than 60% power-added efficiency (PAE) with more than 35.5-dBm output power. The high-band PA achieves 45%-53% PAE across the band with greater than 33.4-dBm output power. Measured linearity performance is presented using an EDGE modulation source. A dc/dc buck converter was also integrated in the PA die as the power management circuitry. Measured results for the output power, PAE, and spurious emissions in the receive band while the dc/dc converter is biasing the PA and running at different modes are reported. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Q -Band and W -Band Power Amplifiers in 45-nm CMOS SOI

    Page(s): 1870 - 1877
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1750 KB) |  | HTML iconHTML  

    The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for Q- and W-bands and a push-pull amplifier is investigated at Q-band. The Q-band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The W-band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Fully Integrated Watt-Level Linear 900-MHz CMOS RF Power Amplifier for LTE-Applications

    Page(s): 1878 - 1885
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1382 KB) |  | HTML iconHTML  

    There is a growing demand for the implementation of the RF power amplifier (PA) in CMOS technologies, due to its cost and integration benefits. Most of the already reported CMOS PAs do not have sufficient output power nor linearity to cope with the long term evolution (LTE) requirements. In this paper, the linearity requirements for power amplifiers targeting LTE-applications are investigated. Based on this system level analysis, a single-chip fully integrated CMOS power amplifier with sufficient power and linearity for emerging E-UTRA/LTE-applications is designed. This 90-nm LTE-band VIII CMOS linear power amplifier uses a distributed active transformer (DAT) as power combiner and delivers an output power up to 29.4 dBm with 25.8% power-added efficiency (PAE) and has 28-dB small-signal gain. The choice of optimal biasing ensures a very flat gain and small AM-PM distortion up to high output power. While applying an uplink LTE signal, the PA produces 25 dBm of average output power with 15% PAE while obeying the stringent EVM-specifications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical Design Methodology of Outphasing Amplification Systems Using a New Simplified Chireix Combiner Model

    Page(s): 1886 - 1895
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2107 KB) |  | HTML iconHTML  

    An analytical design methodology of outphasing amplification systems is proposed using new simplified analytical expressions for the instantaneous efficiency and the input/output voltages of Chireix outphasing combiners. These expressions are derived first for ideal voltage sources with nonzero internal impedance and later for ideal Class-B amplifiers where dc current variation is incorporated. They take into account the impedance mismatch between the amplifiers and the lossless combining structure and account explicitly for the all of the combiner's electrical parameters. We show that the maximum achievable instantaneous combining efficiency can be controlled in position and in value through the judicious choice of the combiner's stub length and transmission-line characteristic impedance. We further show that, when this choice is combined with the amplified signal's distribution, the average combining efficiency can be precisely controlled and easily maximized. Various validations of the proposed expressions are performed by comparison with experimental and simulation results for various combiners as well as for a complete linear amplification with nonlinear components amplifier. Excellent agreement between simulations and measurements is obtained in all cases considered. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Zero-Voltage-Switching Contour-Based Outphasing Power Amplifier

    Page(s): 1896 - 1906
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2048 KB) |  | HTML iconHTML  

    A parallel class-E modified Chireix outphasing power amplifier (PA) that can maintain high efficiency across a wide output power range is presented. The architecture presented essentially implements a zero voltage switching (ZVS) contour-based PA using a modified Chireix outphasing structure. It utilizes the inherent load modulation present in the outphasing scheme and combines it with duty cycle modulation to satisfy ZVS conditions over a wide range of output powers. Thus, a ZVS contour-based PA is realized, and the amplifier maintains high efficiency for about 9-dB back-off of output power. Beyond the 9-dB range, simple outphasing is performed to extend the dynamic range up to about 30 dB. The proposed PA, implemented using discrete components on an FR4 printed circuit board, achieves a dynamic range of 30 dB with a peak power of 29 dBm and a peak drain efficiency of 65% at about 6-dB back-off from the peak output power at 100 MHz from a 3-V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers

    Page(s): 1907 - 1915
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1747 KB) |  | HTML iconHTML  

    This paper presents a direct model structure for describing class-D outphasing power amplifiers (PAs) and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths, and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals' phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch. Model and predistortion performance are evaluated on a 32-dBm peak-output-power class-D outphasing PA in CMOS with on-chip transformers. The excitation signal is a 5-MHz downlink WCDMA signal with peak-to-average power ratio of 9.5 dB. Using the proposed digital predistorter, the 5-MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 to -45.6 dBc. The 10-MHz ACLR was improved by 6.4 dB, from -44.3 to -50.7 dBc, making the amplifier pass the 3GPP ACLR requirements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Investigation of Wideband Load Transformation Networks for Class-E Switching-Mode Power Amplifiers

    Page(s): 1916 - 1927
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2133 KB) |  | HTML iconHTML  

    In this paper, single-ended and differential class-E load transformation networks (LTNs) for wideband operation are investigated. For this purpose, a differential third parallel-tuned tank LTN and a parallel-circuit load LTN without suppressing tanks are proposed to fulfill the class-E wideband condition. The differential parallel-circuit load (DPCL), which considers the finite RF chokes, has higher output resistance, and because of the differential structure, which ensures an open circuit at even harmonic frequencies, it is able to cover a wide frequency range. Consequently, the DPCL is well suited for highly integrated monolithic designs, as well as wideband application. Based on this analysis, a wideband class-E switching-mode power amplifier in CMOS 90 nm using the DPCL is designed. By deliberately combining the LTN with an on-chip balun, a compact size of 1.2 mm2 is achieved. The circuit performance dependency on bond-wire length variation is analyzed and discussed. Measured results show a peak output power of 28.7 dBm, power-added efficiency (PAE) of 48.0%, and drain efficiency of 55.0% at 2.3 GHz. From 1.7 to 2.7 GHz, PAE is higher than 42% and output power is above 25 dBm. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Continuous Inverse Class-F Mode With Resistive Second-Harmonic Impedance

    Page(s): 1928 - 1936
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2052 KB) |  | HTML iconHTML  

    In this paper, an extended version of the continuous class-F-1 mode power amplifier (PA) design approach is presented. A new formulation describing the current waveform in terms of just two additional parameters, while maintaining a constant half-wave rectified sinusoidal voltage waveform, allows multiple solutions of fundamental and second-harmonic impedances that provide optimum performance to be computed. By varying only the imaginary parts of fundamental and second-harmonic impedances, it is shown that output performance in terms of power and efficiency is maintained constant and equal to that achievable from the standard class-F-1 . Indeed, when presenting resistive second-harmonic impedances, it will be demonstrated that the fundamental load can be adjusted to maintain satisfactory output performances greater than a certain predetermined target value. The measurements, conducted on a GaAs pHEMT device at 1 GHz, show a good agreement with the theoretical analysis, revealing drain efficiencies greater than 70% for a very large range of load solutions, which can translate to an ability to accommodate reactive impedance variations with frequency when designing broadband PAs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Behaviors of Class-F and Class- {\hbox {F}}^{-1} Amplifiers

    Page(s): 1937 - 1951
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3804 KB) |  | HTML iconHTML  

    Operational behaviors of the class-F and class-F-1 amplifiers are investigated. For the half-sinusoidal voltage waveform of the class-F-1 amplifier, the amplifier should be operated in the highly saturated region, in which the phase relation between the fundamental and second harmonic currents are out-of-phase. The class-F amplifier can operate at the less saturated region to form a half sinewave current waveform. Therefore, the class-F-1 amplifier has a bifurcated current waveform from the hard saturated operation, but the class-F amplifier operates as a switch at the saturated region for a second harmonic tuned half-sine waveform. To get the hard saturated operation, the fundamental load is very large, more than √2 times larger than that of the tuned load amplifier. The operational behaviors of the amplifiers are explored with the nonlinear output capacitor. Since the capacitor generates a large second harmonic voltage with smaller higher order terms, the class- F-1 amplifier with the nonlinear capacitor can deliver the proper half-sinusoidal voltage waveforms at a lower power, but the effect of the nonlinear capacitor is small for the class-F amplifier. The class-F-1 amplifier delivers the superior performance at the highly saturated operation due to its larger fundamental current and voltage generation at the expense of the larger voltage swing. The simulation results lead to the conclusion that the class-F-1 amplifier with the nonlinear capacitor is suitable topology for high efficiency. However, in the strict sense, the class- F-1 amplifier with the nonlinear capacitor is not the classical class-F-1 amplifier because the voltage-shaping mechanisms and the fundamental load are quite different. We call it the saturated amplifier since the amplifier is the optimized structure of the power amplifier operation at the saturated mode. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Simplified Broadband Design Methodology for Linearized High-Efficiency Continuous Class-F Power Amplifiers

    Page(s): 1952 - 1963
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2452 KB) |  | HTML iconHTML  

    This paper describes the design approach employed for achieving approximated continuous Class-F power amplifier (PA) modes over wide bandwidths. The importance of the nonlinear device capacitance for wave-shaping the continuous Class-F voltage and current waveforms is highlighted, thus reducing the device sensitivity to second and third harmonic impedance terminations. By identifying the high-efficiency regions on the reactance plane for harmonic band placement, the design can be reduced to a fundamental matching problem. The distributed simplified real frequency technique synthesis algorithm can then be utilized to achieve wideband operation. Using a 10-W Cree GaN HEMT device, greater than 70% efficiency has been measured over a 51% bandwidth from 1.45 to 2.45 GHz, with output powers of 11-16.8 W. The nonlinear PA was then linearized using digital predistortion with 20-MHz long-term evolution and 40-MHz eight-carrier W-CDMA excitation signals, to attain adjacent channel power ratios below -53 and -49 dBc, respectively. To the best of the authors' knowledge, the measured results represent the best performance obtained from a broadband switch-mode PA, and the best linearized switch-mode performance using 20- and 40-MHz modulated signals. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New Trends for the Nonlinear Measurement and Modeling of High-Power RF Transistors and Amplifiers With Memory Effects

    Page(s): 1964 - 1978
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3090 KB) |  | HTML iconHTML  

    Power amplifier (PA) behavior is inextricably linked to the characteristics of the transistors underlying the PA design. All transistors exhibit some degree of memory effects, which must therefore be taken into account in the modeling and design of these PAs. In this paper, we will present new trends for the characterization, device modeling, and behavioral modeling of power transistors and amplifiers with strong memory effects. First the impact of thermal and electrical memory effects upon the performance of a transistor will be revealed by comparing continuous wave and pulsed RF large-signal measurements. Pulsed-RF load-pull from the proper hot bias condition yields a more realistic representation of the peak power response of transistors excited with modulated signals with high peak-to-average power ratio. Next, an advanced device modeling method based on large-signal data from a modern nonlinear vector network analyzer instrument, coupled with modeling approaches based on advanced artificial neural network technology, will be presented. This approach enables the generation of accurate and robust time-domain nonlinear simulation models of modern transistors that exhibit significant memory effects. Finally an extension of the X-parameter (X-parameter is a trademark of Agilent Technologies Inc.) behavioral model to account for model memory effects of RF and microwave components will be presented. The approach can be used to model hard nonlinear behavior and long-term memory effects and is valid for all possible modulation formats for all possible peak-to-average ratios and for a wide range of modulation bandwidths. Both the device and behavioral models have been validated by measurements and are implemented in a commercial nonlinear circuit simulator. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Complex-Chebyshev Functional Link Neural Network Behavioral Model for Broadband Wireless Power Amplifiers

    Page(s): 1979 - 1989
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2043 KB) |  | HTML iconHTML  

    The Neural Network (NN) based models are commonly used in power amplifier modeling and predistorter design, and seen as a potential alternative to model and compensate broadband power amplifiers (PAs) having medium- to-strong memory effects along with high-order nonlinearity. In this paper, we propose a novel computationally efficient behavior model based on complex-Chebyshev functional link neural network (CCFLNN) suitable for dynamic modeling of wireless PAs. The CCFLNN exhibits a simpler compact structure than the previously reported NNs and can require less computational burden during the learning process since it uses the complex-valued topology and does not need the hidden layers, which exist in most of the conventional neural-network-based models. The proposed approach utilizes the complex-valued inverse QR-decomposition-based recursive least square algorithm to update the weighting coefficients of the CCFLNN model. The proposed model is comparatively compared with a real-valued focused time-delay NN model and a conventional memory polynomial model with respect to computation complexities and modeling performance. The accurate modeling capacity of the CCFLNN model is demonstrated through a full characteristic (working in the strongly nonlinear region) 170-W class AB amplifier driven by a multicarrier WCDMA signal. Furthermore, the proposed model has been applied for linearizing a real PA in multicarrier application. Results obtained from the measurement clearly show that the proposed digital predistorter can eliminate various intensity in-band and out-of band distortions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Subsampling Feedback Loop Applicable to Concurrent Dual-Band Linearization Architecture

    Page(s): 1990 - 1999
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1881 KB) |  | HTML iconHTML  

    This paper demonstrates an energy-efficient and low-complexity subsampling receiver adopted in the feedback loop of the dual-band power amplifier (PA) linearization architecture. The challenges and issues on finding the valid subsampling frequencies in nonlinear system are discussed, and a systematic approach for finding valid subsampling frequencies is presented. The subsampling-based receiver is applied as a proper solution for the feedback loop of the dual-band linearization architecture. It is shown that the subsampling feedback loop reduces the complexity and the cost of the dual-band linearization architecture. The simulation and measurement results show the proper functionality of the presented technique and demonstrate a good linearization performance. The measurement results show that when using this method, more than 15-dB improvement in normalized mean squared error and more than 17-dB improvement in adjacent channel power ratio are achieved for a wideband class-AB PA, compared with the unlinearized method. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Microwave Theory and Techniques focuses on that part of engineering and theory associated with microwave/millimeter-wave components, devices, circuits, and systems involving the generation, modulation, demodulation, control, transmission, and detection of microwave signals. This includes scientific, technical, and industrial, activities. Microwave theory and techniques relates to electromagnetic waves usually in the frequency region between a few MHz and a THz; other spectral regions and wave types are included within the scope of the Society whenever basic microwave theory and techniques can yield useful results. Generally, this occurs in the theory of wave propagation in structures with dimensions comparable to a wavelength, and in the related techniques for analysis and design..

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dominique Schreurs
Dominique.Schreurs@ieee.org

Editor-in-Chief
Jenshan Lin
jenshan@ieee.org