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IEEE Design & Test of Computers

Issue 1 • Feb. 2012

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Displaying Results 1 - 25 of 27
  • [Front cover]

    Publication Year: 2012, Page(s): C1
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  • IEEE Xplore Digital Library [advertisement]

    Publication Year: 2012, Page(s): C2
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  • Call for papers

    Publication Year: 2012, Page(s): 1
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  • Table of contents

    Publication Year: 2012, Page(s): 2
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  • Departments [Table of Contents]

    Publication Year: 2012, Page(s): 3
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  • The Quest for High-Yield IC Manufacturing

    Publication Year: 2012, Page(s): 4
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  • Message From the Steering Committee

    Publication Year: 2012, Page(s): 5
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  • Guest Editors' Introduction: Yield Learning Processes and Methods

    Publication Year: 2012, Page(s):6 - 7
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  • Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results

    Publication Year: 2012, Page(s):8 - 18
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (695 KB) | HTML iconHTML

    The yield of an integrated circuit (IC) is well known to be a critical factor in the success of an IC in the market place. Achieving high stable yields helps ensure that the product is profitable and meets quality and reliability objectives. When a new manufacturing process is introduced, or a new product is introduced on a mature manufacturing process, yields will tend to be significantly lower t... View full abstract»

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  • An Industrial Study of System-Level Test

    Publication Year: 2012, Page(s):19 - 27
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1001 KB) | HTML iconHTML

    This paper discusses our experience with the advantages of having SLT in an industrial test flow. In addition, the level of correlation of SLT failures to parameters from other testing steps is also studied for an in-production IC in this work to evaluate if the system-level failures of an IC can be identified at other testing steps. Note that the correlation study performed in this paper is not i... View full abstract»

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  • Applying the Model-View-Controller Paradigm to Adaptive Test

    Publication Year: 2012, Page(s):28 - 35
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (719 KB) | HTML iconHTML

    The paper states that adaptive testing has been a focus area for IC testing in the last few years. The “Model-View-Controller”(MVC) architecture has the potential to improve engineering productivity for analysis and application of Adaptive Testing. View full abstract»

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  • Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations

    Publication Year: 2012, Page(s):36 - 47
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB) | HTML iconHTML

    A variety of yield-learning techniques are essential since no single approach can effectively find every manufacturing perturbation that can lead to yield loss. Test structures, for example, can range from being simple in nature (combs and serpentine structures for measuring defect-density and size distributions) to more complex, active structures that include transistors, ring oscillators, and SR... View full abstract»

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  • Concurrent Device/Specification Cause–Effect Monitoring for Yield Diagnosis Using Alternate Diagnostic Signatures

    Publication Year: 2012, Page(s):48 - 58
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1293 KB) | HTML iconHTML

    In this paper, an efficient methodology for die level test-and-diagnosis for Analog/RF circuits is developed. The key contribution of this work lies in the ability to both determine the DUT specifications as well as the underlying Spice-level model parameters from the same DUT test response on a per chip basis, thereby providing quicker and higher diagnostic resolution. The test and diagnosis proc... View full abstract»

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  • Yield learning perspectives

    Publication Year: 2012, Page(s):59 - 62
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    At its core, yield has a simple definition: the fraction of total chips that are good. Yield learning is not about increasing yield for its own sake. Yield learning is about reducing the cost of a good chip. This benefits everyone involved: the company that builds the wafers, the one that sells the chips, and eventually the end user of whatever product the chip goes into. Yield learning is what ke... View full abstract»

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  • IEEE Design & Test of Computers publication information

    Publication Year: 2012, Page(s): 63
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  • IEEE Xplore Digital Library [advertisement]

    Publication Year: 2012, Page(s): 64
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  • Test and Diagnosis for Small-Delay Defects (Tehranipoor, M. et al; 2011) [Book review]

    Publication Year: 2012, Page(s):65 - 67
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  • Patents in the IEEE Standards Process

    Publication Year: 2012, Page(s):68 - 71
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    Presents information on patents as they relate to the IEEE Standards process. View full abstract»

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  • IEEE Xplore Digital Library [advertisement]

    Publication Year: 2012, Page(s): 72
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  • CEDA Currents

    Publication Year: 2012, Page(s):73 - 74
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  • IEEE Xplore Digital Library [advertisement]

    Publication Year: 2012, Page(s): 75
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  • Test Technology TC Newsletter

    Publication Year: 2012, Page(s):76 - 77
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  • IEEE Design & Test of Computers is looking for a New Editor-In-Chief

    Publication Year: 2012, Page(s): 78
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  • Find the latest semiconductor research in IEEE Xplore [advertisement]

    Publication Year: 2012, Page(s): 79
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  • Yield of Black Swans

    Publication Year: 2012, Page(s): 80
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty