By Topic

Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 5 • Date May 2012

Filter Results

Displaying Results 1 - 25 of 28
  • [Front cover]

    Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (371 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (38 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): 729 - 730
    Save to Project icon | Request Permissions | PDF file iconPDF (83 KB)  
    Freely Available from IEEE
  • Ni Barrier-Induced Cracks in Matte Sn Films

    Page(s): 731 - 738
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3606 KB) |  | HTML iconHTML  

    A nickel barrier layer between a matte tin film and a C194 substrate has been used to prevent whisker formation on the tin surface by blocking the formation of Cu6Sn5 intermetallics, which is one of the root causes of whisker growth. However, the introduction of the Ni barrier to the matte Sn/C194 system greatly changes the mechanical properties of the bended leads. In this paper, the effect of a Ni barrier on the mechanical stability of matte tin films deposited onto C194 leads of an SOIC-8 package is investigated. Backscattered electron imaging and focused ion beam imaging of the cross-section samples indicate that, during the forming process, the surface cracks in the matte tin films often initiate and propagate from the Ni barrier, which lacks cooperative deformation ability in comparison with the ductile copper alloy substrate and the matte tin film. The thicker Ni barrier could induce considerable mechanical damage to the matte Sn films of the integrated circuit package after reflow treatment due to the coefficient of thermal expansion mismatch. The thermal-humidity testing of the Sn/Ni/C194 samples reveals that the surface cracks formed may be attributed to the built-in tensile stress arising from the formation of Ni3Sn4 intermetallic compounds (IMCs). A thinner Ni barrier layer can withstand the forming stress, thermal mismatch stress, and IMC-induced stress without causing cracks in the matte Sn films and does not promote Sn whisker growth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparative Study of Metal Films and Their Affinity for Metal Whisker Growth

    Page(s): 739 - 747
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7630 KB) |  | HTML iconHTML  

    The problem of tin (Sn) whiskers has been a significant reliability issue in electronics for the past several decades. Despite the large amount of research conducted on this issue, the growth of whiskers remains a challenge for the research community. A comparative study of different metal whiskers could provide a deeper insight toward the development of more permanent mitigation strategies for Sn whisker growth. In this paper, the surface and microstructural evolution of various film/substrate combinations of 10-μm thick zinc (Zn) and Sn metal films and their affinity for whisker growth were observed under two environmental conditions-ambient temperature and elevated temperature of 55°C and 85% humidity. The films were analyzed using a scanning electron microscope, focused ion beam, and electron dispersive spectroscope. In addition, several decades-aged samples with Zn, Sn, and cadmium films with a high density population of whiskers were observed for comparison. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solder-Joint Quantitative Crack Analysis—Ohmic Resistance Approach

    Page(s): 748 - 755
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (793 KB) |  | HTML iconHTML  

    This paper presents a novel technique in the area of solder-joint reliability testing, suggesting a new approach for efficient testing of new products. An analytical model was developed relating the solder-joint ohmic resistance and the joint crack's length caused by temperature cycles. Based on the analytical model, a technique was developed allowing the measurement of a solder-joint's crack length in a nondestructive, continuous way. Thus, prediction of the solder-joint's end-of-life could be done at an early stage of the test, which substantially reduces the test time. This technique of resistance monitoring was validated with a commonly used test vehicle utilizing commercially off-the-shelf daisy-chain quad flat no-lead (QFN44) package. This method is not limited to lab tests, but rather is applicable also for prognostics and preventive maintenance in deployed products. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel Self-Assembly Process Using Magnetically Aligned z -Axis Anisotropic Conductive Adhesive for High-Density Vertical Interconnection

    Page(s): 756 - 763
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1868 KB) |  | HTML iconHTML  

    In this paper, a novel self-assembly packaging approach using a magnetically aligned z -axis anisotropic conductive adhesive (ACA) is introduced, enhancing the quality of interconnects and reducing packaging cost in fine-pitch electronic circuitry. This self-assembly process creates selectively agglomerated vertical columns on I/O pads and is first demonstrated using the magnetization interaction properties between ferromagnetic conductive particles and I/O pads in the presence of an external magnetic field. Experimentally, this packaging process is verified to be particularly beneficial in improving the environmental reliability of the self-aligned material. At 133 × 133-μm pad size, the resistance of the created interconnects only varies by 2.45 Ω over a 160°C temperature range. In addition, the breakdown current of the self-assembly z-axis ACA was measured to be 2.0 A at 1.3 V. Furthermore, this self-assembly process was demonstrated to still work at the extremely small pad size of 12×19-μm. Finally, through analysis of the design parameters of this self-assembly process, properties of the z-axis ACA material and I/O pad structure were suggested to create vertical interconnects for small pads of size in the order of 10 μm. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal Chip Placement in MCMs Using a Novel Hybrid Optimization Algorithm

    Page(s): 764 - 774
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (772 KB) |  | HTML iconHTML  

    This paper reports on enhancing the thermal performance of multiple-chip modules (MCMs) that contain a number of chips under natural convection by optimizing the chip placement layout. To attain this goal, an innovative hybrid optimization approach (HOA) incorporating a genetic algorithm (GA) into an algorithm based on a response surface method (RSM) is introduced for improving the performance of both these algorithms. The GA in the proposed HOA is responsible for not only evolving the population toward better fitness value but also, based on the newly evolved populations at each GA generation, for continuously updating the RS mathematical model for better approximation of the chip junction temperature. The sum of the mathematical expressions representing the total system temperature defines the objective of the optimization problems. For each GA generation, a constrained quadratic optimization subproblem is formed, based on the newly updated approximate RS mathematical model as the objective function along with the specified constraints. The solution of the optimization subproblem is sought through a mathematical programming model. As the genetic RS optimization progresses, a sequence of approximate solutions associated with the continuously updated RS mathematical models is constructed. The iterative process continues until convergence of the approximate solutions is attained. To demonstrate the effectiveness of the developed algorithm, several thermal design problems associated with two types of MCMs with equal/unequal power are performed. The obtained results are compared with those derived using two conventional approaches-the GA-based and the RSM-based optimization techniques. Results show that the developed algorithm can provide good optimal solutions with much less computational effort, and the larger the scale of the design problems, the more significant the improvement in the computation cost. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Self-Packaged Millimeter-Wave Substrate Integrated Waveguide Filter With Asymmetric Frequency Response

    Page(s): 775 - 782
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1588 KB) |  | HTML iconHTML  

    Substrate integrated waveguide (SIW) technology provides an effective solution for the low-cost and high-performance interconnect and packaging of microwave and millimeter wave systems. In this paper, Ka-band four-degree bandpass filters having asymmetric frequency response, which are required in the design of transmit and receive diplexers for high rejection between neighboring channels, are proposed and realized on an SIW platform. The filters are self-packaged due to the fact that a conductor-backed coplanar waveguide is used to directly excite the filters. Higher-order resonant mode is used to achieve the required negative coupling on the basis of a single-layer SIW. The proposed filters, having the same center frequency of 35 GHz and pass bandwidth of 1.3 GHz, are fabricated on a conventional Rogers RT/Duroid 6002 substrate with thickness of 0.508 mm by using a low-cost printed circuit board process. Measured results of those filters, which exhibit high single-sided selectivity and minimum in-band insertion loss of about 1.25 dB, agree well with simulated results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Alternating Direction Explicit-Latency Insertion Method (ADE-LIM) for the Fast Transient Simulation of Transmission Lines

    Page(s): 783 - 792
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB) |  | HTML iconHTML  

    This paper describes the alternating direction explicit-latency insertion method (ADE-LIM) for the fast simulations of transmission lines. LIM is one of the fast transient analysis techniques for large networks. However, because this method is based on an explicit finite-difference method, it has a limitation of the time step size for the numerical stability condition similar to the finite-difference time-domain technique. On the other hand, the ADE method is one of the finite-difference methods and has advantages of less computational complexity and numerical stability. In this paper, we propose ADE-LIM as an improved method of LIM. This method can circumvent the above time step limitation problem because the method is based on the ADE algorithm. Numerical results show that ADE-LIM is about 3-3.5 times faster than LIM in the transmission line analyses with appropriate accuracy. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mold-Free in Situ Formation of Encapsulating Lens With Controllable Viewing Angle for LEDs by Photosensitive Polymerization Process

    Page(s): 793 - 798
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (414 KB) |  | HTML iconHTML  

    Using photosensitive epoxy resin liquids as encapsulation materials, a mold-free encapsulation technology is developed in this paper to form lenses on light emitting diode (LED) chips with controllable viewing angles. The light emitted by the LED itself is used to trigger polymerization of photosensitive resins. The shapes of the encapsulation lens are controlled by the “nucleus” formed in the initial stage and by the surface tension of the photosensitive resin liquid. LED packages with viewing angles of 90° and 165° are fabricated in this paper as examples. Encapsulations with other viewing angles are expected to be achievable when using liquids of corresponding surface tension. The whole packaging process can be completed within 20 min, or even less, at room temperature and normal pressure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Encapsulation of Microelectronic Components Using Open-Ended Microwave Oven

    Page(s): 799 - 806
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (659 KB) |  | HTML iconHTML  

    An open-ended microwave oven system is presented and characterized for the rapid encapsulation of microelectronic components. In situ real-time measurement of the temperature of the curing materials is carried out by an infrared pyrometer integrated in the microwave head of the oven. An automatic computer-controlled closed feedback loop has been used to measure the temperature in the curing material and modulate the system operating power to obtain predefined curing temperature cycles for efficient curing. Uniform curing of the encapsulant material is achieved with typical cure time of ~300s with a ramp rate of 1.66°C/s and a hold period of ~100s . Differential scanning calorimeter based measurement for the curing of the polymer dielectric indicates a near 100% degree of cure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of Packaging Design on Reliability of Large Die Cu/Low- \kappa (BD) Interconnect

    Page(s): 807 - 816
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1576 KB) |  | HTML iconHTML  

    This paper presents the study on the effect of low-κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low-κ chip for improving assembly and reliability performance on organic buildup substrate flip chip ball grid array (FCBGA). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hybrid Liquid Immersion and Synthetic Jet Heat Sink for Cooling 3-D Stacked Electronics

    Page(s): 817 - 824
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB) |  | HTML iconHTML  

    This paper focuses on the design and parametric numerical study of a hybrid heat sink combining a liquid thermal interface with an array of synthetic jet actuators for 3-D chip stack cooling. The air-side heat sink exploits enhanced localized heat transfer achieved via a central array of synthetic jet actuators. The key focus of this paper is the numerical simulation of the dielectric liquid interface used to efficiently transmit the heat from the high-power 3-D stacked electronics to the hybrid heat sink base. The coupled natural convection in the fluid and conduction in solid spreaders sandwiched between the tiers of the stack form a novel efficient, passive, and scalable thermal management solution for 3-D stacked die structures. It is shown that this heat sink with a footprint of 76-mm square × 51-mm height can dissipate a total of 41 W of heat/power from the stack for a 44°C average chip temperature rise above ambient (an Rja of ~ 1.06 K/W obtained passively). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Numerical Analysis of Novel Micro Pin Fin Heat Sink With Variable Fin Density

    Page(s): 825 - 833
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (938 KB) |  | HTML iconHTML  

    Numerical analyses to characterize and design micro pin fin heat sinks for cooling the 2016s IC chip heat generation are carried out in this paper. A novel design with variable fin density is proposed to generate a more uniform temperature of the IC chip junctions. The variable-density feature allows the gradual increase of the heat transfer area as coolant passes through the system. Single-phase water in the laminar regime is employed. Four different fin shapes (circle, square, elliptical, and flat with two redounded sides) are analyzed. The junction temperature and pressure drop variations in the heat sink generated by these shapes are presented. The effects of varying the fin length and height are also studied. The best heat sink configuration has a thermal resistance ranging from 0.14 to 0.25 K/W with a pressure drop lower than 90 kPa and a junction temperature ~ 314 K under the conditions studied. The temperature gradient at the bottom wall of the heat sink is considered as a parameter for comparing various heat sink designs. The novel cooling device has an overall temperature gradient lower than 2°C/mm, which is significantly lower than the temperature gradients in other schemes reported in literature. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Measurement and Analysis for Residual Warpage of Chip-on-Flex (COF) and Chip-in-Flex (CIF) Packages

    Page(s): 834 - 840
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1067 KB) |  | HTML iconHTML  

    A flip-chip package using adhesive interconnection consists of materials which have different coefficients of thermal expansion (CTE). The package experiences temperature higher than room temperature during the assembly process and is also exposed to the thermal cycling load during its lifetime. As a result, flip-chip packages have residual warpage after completion of the assembly process. Excessive warpage causes various reliability problems. Therefore, residual warpage is an essential factor for evaluating the reliability of electronic packages. In this paper, we evaluated the warpage of chip-on-flex (COF) packages using the moiré methods. A chip-in-flex (CIF) package developed to increase the binding force between the chip and the substrate was also evaluated with the same methods. Finite element analysis (FEA) was also performed for comparison with the experimental results. Based on the FEA result, effective design parameters for the CIF package were found to reduce the residual warpage. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact High-Gain mmWave Antenna for TSV-Based System-in-Package Application

    Page(s): 841 - 846
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (847 KB) |  | HTML iconHTML  

    This paper presents a cavity-backed slot (CBS) antenna for millimeter-wave applications. The cavity of the antenna is fully filled by polymer material. This filling makes the fabrication of a silicon CBS antenna feasible, reduces the cavity size by 76.8%, and also maintains the inherent high-gain and wide bandwidth. In addition, a through-silicon via-based architecture is proposed to integrate the 135-GHz CBS antenna with active circuits for a complete system-in-package. Results show that the proposed structure not only reduces the footprint size but also suppresses the electromagnetic interference. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transmission Performances of CPW Lines on a Laser-Crystallization Polysilicon Passivated High-Resistivity Silicon Substrate

    Page(s): 847 - 851
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (695 KB) |  | HTML iconHTML  

    In this paper, we report the preparation of polycrystalline silicon by excimer laser-crystallization of amorphous silicon α and its use as a surface-passivation layer (SPL) on high-resistivity silicon (HR-Si) substrates. The transmission loss (αTL) of coplanar waveguide (CPW) lines on an oxide-coated HR-Si substrate with a 100-nm excimer laser-annealed (ELA) SPL is less than 1.16 dB/cm at frequencies up to 20 GHz. Therefore, an ELA-SPL is capable of providing good surface passivation for radio-frequency integrated circuit applications. The influence of geometric parameters on the transmission characteristics of the CPW lines is also studied. Extracted material parameters and equivalent lumped elements are used to interpret the loss mechanisms. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication

    Page(s): 852 - 859
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1700 KB) |  | HTML iconHTML  

    3-D integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3-D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3-D integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting “decap” die and through-vias, are discussed in this paper. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal Terminations for Crosstalk Mitigation of High-Speed Interconnects With Discontinuities Using Modal Signaling

    Page(s): 860 - 867
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1440 KB) |  | HTML iconHTML  

    In high-speed chip-to-chip single-ended signaling links, far-end crosstalk presents one of the dominant noise sources, limiting the link performance. Diagonalizing the channel using modal decomposition has been proposed to mitigate the crosstalk. However, special attention needs to be devoted to the frequency dependence of optimal modal matching terminations used in modal signaling. In this paper, application of modal decomposition to a typical memory bus with discontinuities is presented. The properties of the modes are closely studied to construct the frequency-dependent optimum terminations, which are then synthesized using low-order passive RLC networks. The proposed approach is verified using statistical link simulation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Drop-on-Demand Laser Sintering With Silver Nanoparticles for Electronics Packaging

    Page(s): 868 - 877
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2005 KB) |  | HTML iconHTML  

    This paper proposes a “dry” laser-sintering method and discusses characteristics of a laser-sintered silver thin film on a polyimide or a copper substrate. This novel technology consists of the following processes: first, ink-jet printing of metal nanoparticles with dispersants and solvents for minute patterning; second, short preheating to remove organic substances in the ink; and finally, millisecond-order laser-beam irradiation under atmospheric conditions with the flow of argon gas for metallization. Regarding the wiring, visible lasers with high absorption on the ink develop rapid metallization and activate solvent evaporation, resulting in a rough surface with large pores. Interface adhesion is increased by the anchoring effect in the course of laser irradiation. In contrast, near-infrared lasers with low absorption heat the ink from the polyimide interface, yielding a dense, low-specific-resistance structure. Regarding pad formation on the copper leadframe without any surface pre-treatments, interdiffusion takes place at the Ag/Cu interface and increases adhesivity. The structural quality of the laser-sintered silver pad is almost the same as that of an electroplated one, so that no difference in good wire-bondability is obtained when the near-infrared continuous-wave laser is irradiated for a short time of a millisecond order per lead. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Affordable Ink-Jet Printed Antennas for RFID Applications

    Page(s): 878 - 883
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (566 KB) |  | HTML iconHTML  

    With the increasing demands of radio-frequency identification (RFID) applications, an alternative ink-jet printing technique for RFID tag antenna is demonstrated. Commercially available ink-jet printers are adapted for conductive printing, in order to minimize manufacturing cost. Paper-based dipole antenna and dipole with a tuning stub antenna were designed. The antennas were ink-jet printed and assembled with RFID chips. The performances of the fabricated tags were measured through the reading range. With reference to equivalent isotropically radiated power of 4 W at 923 MHz, the reading range of tag with dipole antenna is around 9 m and of tag with dipole with a tuning stub is nearly 13 m. These performances are comparable to those of commercial tags. The advantages of the proposed printing technique are simplicity, flexibility and, more importantly, affordability. The technique can, in addition, contribute to further development and enhance extension of RFID applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ultrasonic Bonding of Anisotropic Conductive Films Containing Ultrafine Solder Balls for High-Power and High-Reliability Flex-On-Board Assembly

    Page(s): 884 - 889
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (883 KB) |  | HTML iconHTML  

    New solder anisotropic conductive films (ACFs) consist of a thermosetting polymer resin and fine solder balls instead of the conventional metal particles or metal-coated polymer particles. These solder balls have lower melting temperature than conventional metal conductive particles, which enable them to be melted during ultrasonic (US) bonding, and form intermetallic alloy joints with metal pads of flex on board. In this paper, excellent solder ACF joints are demonstrated using a US-bonding method for high-power and high-reliability flex-on-board (FOB) assemblies. Ultrasonically bonded solder ACF joints were characterized in terms of their electrical properties and reliability. Solder alloy bonding was achieved using two kinds of solder balls, i.e., Sn-58Bi and SAC305 (96.5Sn-3.0Ag-0.5Cu). At the same time, the acrylic ACF resin was completely cured after 5 s of US bonding. Solder alloy ACF joints show about 20% decrease in daisy-chain electrical resistance and 100% increase in the current-carrying capability compared with conventional physical-contact-based Ni ACF joints. Solder alloy ACF joints also show significantly improved reliability with stable electrical resistances up to 24 h in an unbiased autoclave test, whereas conventional Ni ACF joints show severe electrical open failures within 4 h. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Blank page]

    Page(s): 890
    Save to Project icon | Request Permissions | PDF file iconPDF (5 KB)  
    Freely Available from IEEE
  • IEEE Xplore Digital Library [advertisement]

    Page(s): 891
    Save to Project icon | Request Permissions | PDF file iconPDF (1347 KB)  
    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

Full Aims & Scope

Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University