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Semiconductor Manufacturing, IEEE Transactions on

Issue 2 • Date May 2012

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Displaying Results 1 - 24 of 24
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): C2
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  • Special Section on the International Conference on Microelectronic Test Structures

    Page(s): 129
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  • Array Test Structures for Gate Dielectric Integrity Measurements and Statistics

    Page(s): 130 - 135
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5880 KB) |  | HTML iconHTML  

    An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the stress induced degradation of transistor parameters. The test array has been fabricated in a standard mixed-mode 130 nm CMOS technology. As such technologies offer both thin and thick gate dielectrics for MOS transistors, different gate dielectric thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages and prevent the control logic from degradation. View full abstract»

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  • Test Structure for High Voltage LD-MOSFET Device Mismatch Investigations

    Page(s): 136 - 144
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7851 KB) |  | HTML iconHTML  

    A characterization setup for high voltage (HV) LD-MOSFET mismatch and variability determination is presented. Devices are aligned in rows and columns for gate and drain bias multiplexing and special HV-switches for voltages up to 50 V are controlled by externally generated digital signals. Automatic DC measurements can be performed on up to 4992 HV-NMOSFETs. The circuit designs of the HV-switches are described in detail and characterization data gained during functionality evaluation are presented. Variability data are provided for both short and long distance matching characterization. View full abstract»

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  • A Simple Test Structure for Evaluating the Variability in Key Characteristics of a Large Number of MOSFETs

    Page(s): 145 - 154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12411 KB) |  | HTML iconHTML  

    The increase in the electrical characteristic variability of MOSFETs caused by the miniaturization of MOSFETs is one of the critical issues for realizing the low power consumption of large-scale-integrated circuits and the high accuracy of analog devices. It is necessary to easily evaluate the variability of a very large number of MOSFETs in a very short time for short-period-developing fabrication processes and device structures. We have proposed and developed a simple test structure for evaluating the electrical characteristics of over 1.2 million MOSFETs such as threshold voltage (Vth), subthreshold swing (S-factor) in around 30 min. The accuracy of the test circuit developed is 1.9 mV, as 3σ. We have also evaluated the Vth distribution, the S-factor distribution, and the dependence of Vth variability on the gate size and antenna ratio of MOSFETs. The measurement results are very useful in developing fabrication processes, process equipment, and device structures, that suppress the variability. View full abstract»

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  • Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS

    Page(s): 155 - 161
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8433 KB) |  | HTML iconHTML  

    Device scaling of partially depleted (PD) silicon-on-insulator (SOI) has the potential to increase speed. However, the increased gate tunneling and capacitance will complicate device behaviors and increase the difficulty in characterization for modeling purpose. For the first time, gate-bulk leakage current Igb and gate capacitance Cgg characterization methodology for PD SOI floating-body (FB) CMOS with high accuracy is proposed and verified in 40-nm SOI devices. These devices are with ultrathin equivalent oxide thickness of 12Å, and radio frequency-capacitance voltage (RF-CV) technique is used for Cgg measurement to overcome the impact of leaky gate current. This methodology can eliminate properly the parasitic elements due to the coexistence of opposite poly gate type in the SOI T-shape body-tied device and accurately characterize and model Igb and Cgg behaviors for the PD SOI FB devices. Test patterns are designed with RF ground-signal-ground configuration and same test patterns can be used for both Igb and Cgg characterization. Impact of Igb and Cgg changes on the history effect, and speed and body potential is analyzed by BSIMSOI4.0 models. Simulation accuracy of history effect will have at least 3% improvement with this proposed methodology. View full abstract»

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  • Electrical Test Structures for the Characterization of Optical Proximity Correction

    Page(s): 162 - 169
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5541 KB) |  | HTML iconHTML  

    Resistive electrical test structures have been designed to enable the characterization of optical proximity correction (OPC) applied to a right-angled corner in a conducting track. The OPC consists of square serifs that are either added to the outside corner or subtracted from the inner corner. Varying degrees of OPC can be applied by changing the size of the square serif or by changing the amount by which it encroaches on or protrudes from the corner. A prototype test mask has been fabricated that contains test structures suitable for on-mask electrical measurement. The same mask was used to print the test pattern in polysilicon and aluminium using an i-line lithography tool and results from these structures clearly show that OPC has an impact on the resistance of the final printed features. In particular, the level of corner rounding is dependent upon the dimensions of the serifs employed and the measured resistance can be used to characterize the effects of different levels of OPC applied to the inner corners. View full abstract»

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  • In Situ Silicon-Integrated Tuner for Automated On-Wafer MMW Noise Parameters Extraction Using Multi-Impedance Method for Transistor Characterization

    Page(s): 170 - 177
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12591 KB) |  | HTML iconHTML  

    In this paper, the design and use of an in situ tuner (IST) aiming On-Wafer multi-impedance method are presented. The conventional method using Off-Wafer tuner is limited by the frequency range and has high losses between this external tuner and the device under test (DUT). Here, the IST is placed near the DUT to achieve higher |Γ| and to cancel losses between the impedance generator and the device. The architecture of the tuner is based on variable lumped R and C elements fulfilled with cold-field-effect transistor and varactors controlled through biasing and associated to coplanar transmission line for phase shifting. Detailed and dedicated noise de-embedding technique is described to extract the four noise (NFmin, Rn, Γopt) parameters of 65-nm metal-oxide-semiconductor field-effect silicon transistors through the use of this in situ multi-impedance method. The 75-110 GHz noise test bench using cold-noise source method and the noise measurement are described showing transistor capabilities at MMW. View full abstract»

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  • Four Point Probe Structures With Buried and Surface Electrodes for the Electrical Characterization of Ultrathin Conducting Films

    Page(s): 178 - 184
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6934 KB) |  | HTML iconHTML  

    Test structures for the electrical characterization of ultrathin conductive films are presented based on electrodes on which the ultrathin film is deposited. Two different designs are discussed: a novel design with buried electrodes and a conventional design with electrodes at the surface. This paper includes test structure design and fabrication, and the electrical characterization of atomic layer deposition TiN films down to 4 nm. We demonstrate that the novel test structures provide the same results as the conventional structures, and have the advantage of broader materials choice (i.e., conductor-dielectric combination). The proposed structures can be used successfully to characterize sub-10 nm films. View full abstract»

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  • Changes in the Editorial Board

    Page(s): 185
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  • An Efficient Mixed Integer Programming Model Based on Timed Petri Nets for Diverse Complex Cluster Tool Scheduling Problems

    Page(s): 186 - 199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3586 KB) |  | HTML iconHTML  

    Cluster tools are automated production cells which are largely used for semiconductor manufacturing. They consist of several processing modules (PMs) and a transportation robot. Since cluster tools have limited buffers and diverse scheduling requirements such as complex wafer flow patterns, parallel PMs, wafer residency time constraints, and dual-arm robot, and so on, their scheduling problems are difficult. Due to the diversity of scheduling problems, dealing with those problems one by one may be impractical. Computational complexity is another difficulty. In this paper, we propose an efficient scheduling method to deal with diverse complex cluster tool scheduling problems by using timed Petri nets (TPN). We propose TPN models of cluster tools with various scheduling requirements. Then, based on the TPN models and their state equations, we develop a new mixed integer programming (MIP) model that can efficiently determine the optimal cyclic schedules. We show that many kinds of scheduling requirements such as parallel, reentrant and multiple material flows, a dual-armed robot, and time constrained PMs can be dealt with by the MIP model. Through experiments, we also show that the MIP model can efficiently solve most practical cluster tool scheduling problems. View full abstract»

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  • Multiproduct Lot Merging–Splitting Algorithms for Semiconductor Wafer Fabrication

    Page(s): 200 - 210
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1011 KB) |  | HTML iconHTML  

    This paper focuses on a lot merging-splitting problem in a semiconductor wafer fabrication facility in which a relatively large number of wafer types are produced according to orders with different due dates. In the fab, two or more lots can be merged into a single lot if routes and all processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging-splitting algorithms to reduce the total tardiness of the orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab. View full abstract»

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  • Equilibria, Stability, and Transients in Re-Entrant Lines Under FBFS and LBFS Dispatch and Constant Release

    Page(s): 211 - 229
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12716 KB) |  | HTML iconHTML  

    A model of a re-entrant line, consisting of the bottleneck workcenter and time delays representing other workcenters, is considered. Its mathematical description is provided and performance metrics are introduced. The steady states of this model and their stability properties are investigated under two dispatch policies-first buffer first served (FBFS) and last buffer first served (LBFS)-and under constant release rate. The transients due to machine downtime are also analyzed. It is shown that, although LBFS may be viewed as having superior steady-state characteristics, it induces longer and more volatile transients than FBFS and, in some cases, periodic and chaotic regimes. View full abstract»

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  • An Adaptive-Tuning Scheme for G&P EWMA Run-to-Run Control

    Page(s): 230 - 237
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6970 KB) |  | HTML iconHTML  

    Run-to-run (RtR) control is an important method for improving process capability. The most common form of RtR controllers are exponentially weighted moving average (EWMA) controllers. The performance of EWMA RtR controllers is affected by the values of the selected tuning parameter. In practice, the tuning parameter usually remains unchanged, resulting in suboptimal performance. In this paper, we propose an adaptive-tuning method for a group and product (G&P) EWMA controller to improve the control performance. The G&P EWMA controller is developed for mixed run processes. We show that the optimum-tuning parameters for the next run of this G&P EWMA controller are obtained online using a window of historical input-output data. The performance improvement due to the proposed method is demonstrated by a simulation example and an industrial application. View full abstract»

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  • Dynamic-Moving-Window Scheme for Virtual-Metrology Model Refreshing

    Page(s): 238 - 246
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9826 KB) |  | HTML iconHTML  

    Virtual metrology (VM) is a method to conjecture manufacturing quality of a process tool based on data sensed from the process tool without physical metrology operations. Historical data is used to produce the initial VM models, and then these models are applied to operating in a process drift or shift environment. The accuracy of VM highly depends on the modeling samples adopted during initial-creating and online-refreshing periods. Since large resources are required, design-of-experiments may not be performed. In that case, how could we guarantee the stability of the models and predictions as they move into the unknown environment? Conventionally, static-moving-window (SMW) schemes with a fixed window size are adopted in the online-refreshing period. The purpose of this paper is to propose a dynamic-moving-window (DMW) scheme for VM model refreshing to enhance prediction accuracy. The DMW scheme adds a new sample into the model and applies a clustering technology to do similarity clustering. Next, the number of elements in each cluster is checked. If the largest number of the elements is greater than the predefined threshold, then the oldest sample in the cluster with the largest population is deleted. Both the adaptive-resonance-theory-2 and the newly proposed weighted-Euclidean-distance methods are applied to do similarity clustering. View full abstract»

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  • Characterization and Modeling of Atomic Layer Deposited High-Density Trench Capacitors in Silicon

    Page(s): 247 - 254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5640 KB) |  | HTML iconHTML  

    A detailed electrical analysis of multiple layer trench capacitors fabricated in silicon with atomic-layer-deposited Al2O3 and TiN is presented. It is shown that in situ ozone annealing of the Al2O3 layers prior to the TiN electrode deposition significantly improves the electric properties of the devices such as the dielectric constant, leakage current, and the breakdown voltage of the devices. The self-inductance and self-resistance of the capacitors as derived from S-parameter measurements up to 10 GHz are very small, as low as 4 pH and 6 mΩ for 19.1 mm2 electrode surface. These data are shown to be consistent with a theoretical model. View full abstract»

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  • Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations

    Page(s): 255 - 265
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8576 KB) |  | HTML iconHTML  

    Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances. View full abstract»

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  • Random Work-Function-Induced Threshold Voltage Fluctuation in Metal-Gate MOS Devices by Monte Carlo Simulation

    Page(s): 266 - 271
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6290 KB) |  | HTML iconHTML  

    In this paper, we estimate the effect of random work function (WK) on the threshold voltage fluctuation (σVth) of 16-nm-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with metal-gate materials. To examine the random WK induced σVth, nanosized metal grains with different gate materials are considered in a large-scale statistical simulation. An analytical expression of the WK induced σVth is proposed based on the Monte Carlo simulation results which can outlook different extents of fluctuation resulting from various metal gates and benefit the device fabrication. Devices with a two-layer metal-gate are further studied for fluctuation suppression; the finding of this paper indicates the first layer of the gate structure plays the most significant role in the suppression of the WK induced σVth, compared with the second layer. This paper provides an insight into random work-function-induced threshold voltage fluctuation, which can, in turn, be used to assess metal gate characteristics of MOSFETs. View full abstract»

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  • Generalized Inference for Measuring Process Yield With the Contamination of Measurement Errors—Quality Control for Silicon Wafer Manufacturing Processes in the Semiconductor Industry

    Page(s): 272 - 283
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2568 KB) |  | HTML iconHTML  

    The yield index Spk provides an exact measure of process yield for normally distributed processes, and it has been popularly accepted by many engineers and shop floor controllers as communication tools for evaluating and improving the manufacturing quality. Most research works related to Spk are carried out under the assumption of no gauge measurement errors. Unfortunately, such an assumption does not accommodate real situations closely even with modern and highly sophisticated measuring instruments. Conclusions drawn from process capability analysis without considering measurement errors are hence unreliable. Recently, Wang studied the impact of the process yield estimation and judgment on the true process yield in the presence of measurement errors and indicated that the presence of measurement errors in the data leads to different behaviors of the estimator according to the entity of the contamination degree. To remedy this, this paper applies the concept of generalized pivotal quantities to construct generalized confidence intervals for Spk with consideration of measurement errors. A series of simulations was undertaken to evaluate the performance of the proposed generalized inference method. The results reveal that the generalized inference method performs very well for measuring process yield in the presence of measurement errors. View full abstract»

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  • Measuring the Manufacturing Yield for Processes With Multiple Manufacturing Lines

    Page(s): 284 - 290
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3154 KB) |  | HTML iconHTML  

    Process yield is the most common criterion used in the semiconductor manufacturing industry for measuring process performance. In the globally competitive manufacturing environment, photolithography processes involving multiple manufacturing lines are quite common in the Science-Based Industrial Park in Hsinchu, Taiwan, due to economic scale considerations. In this paper, we develop an effective method for measuring the manufacturing yield for photolithography processes with multiple manufacturing lines. Exact distribution of the estimated measure is analytically intractable. We obtain a rather accurate approximation to the distribution. In addition, we tabulate the lower conference bounds based on the obtained approximated distributions for the convenience of industry applications. We also develop a decision-making method for process precision testing to determine whether a process meets the process yield requirement preset in the factory. For illustration purposes, an application example is included. View full abstract»

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  • 38th IEEE Photovoltaic Specialists Conference

    Page(s): 291
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    Freely Available from IEEE
  • 2012 IEEE Bipolar/Bicmos Circuits and Technology Meeting (BCTM)

    Page(s): 292
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  • IEEE Transactions on Semiconductor Manufacturing information for authors

    Page(s): C3
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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721