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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 2012

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Displaying Results 1 - 25 of 28
  • Table of contents

    Publication Year: 2012 , Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2012 , Page(s): C2
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  • Table of contents

    Publication Year: 2012 , Page(s): 1069 - 1070
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  • New Associate Editors

    Publication Year: 2012 , Page(s): 1071 - 1072
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  • Overview for the Special Section on the 2011 Radio Frequency Integrated Circuits (RFIC) Symposium

    Publication Year: 2012 , Page(s): 1073 - 1074
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  • Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses

    Publication Year: 2012 , Page(s): 1075 - 1083
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1866 KB) |  | HTML iconHTML  

    In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices. View full abstract»

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  • A 30-MHz–2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems

    Publication Year: 2012 , Page(s): 1084 - 1093
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1710 KB) |  | HTML iconHTML  

    A 30-MHz-2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, results in wideband interference rejection. The energy detector with programmable rectifiers provides dynamic-range (DR) scalability, enabling shared use for white-space/interference-level detection and automatic gain control. A prototype chip, fabricated using 90-nm CMOS technology, achieved over 42-dB harmonic rejection including 7th-order component without any external device, a 67-dB gain, a 5-8-dB noise figure, a -11-dBm in-band third-order intercept point, and a +38-dBm second-order intercept point while drawing only 25-37 mA from a 1.2-V power supply. Multi-resolution DR-scalable spectrum sensing with a 0.2-30-MHz detection bandwidth, -83-dBm minimum sensitivity, and a 29-48-dB DR was demonstrated. View full abstract»

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  • A Low Power Inductorless LNA With Double {\rm G} _{\rm m} Enhancement in 130 nm CMOS

    Publication Year: 2012 , Page(s): 1094 - 1103
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2408 KB) |  | HTML iconHTML  

    This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several gm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic gm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 dBm for an input compression point of -21 dBm. View full abstract»

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  • Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications

    Publication Year: 2012 , Page(s): 1104 - 1112
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2075 KB) |  | HTML iconHTML  

    A digitally-controlled polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented in a 0.15 μm RF CMOS process. Stacked FETs in a current-mode class-D configuration are used to obtain high breakdown voltage and high efficiency in the output stage, and a doughnut-shaped Guanella reverse balun is applied to achieve a 1-to-4 impedance transformation with less than 1 dB insertion loss. The amplifier has 31 dBm output power with 51% drain efficiency at 0.75 GHz frequency under single tone testing. The output stage is fed by a buck converter employing digital pulsewidth modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5% was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power. View full abstract»

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  • A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters

    Publication Year: 2012 , Page(s): 1113 - 1122
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1982 KB) |  | HTML iconHTML  

    In this work, we have demonstrated a fully-integrated, high-efficiency CMOS inverse Class-D PA. Such efficient switching amplifiers can form the core of mixed-signal polar transmitters. A comprehensive analytical framework has been developed to determine optimum component values to maximize efficiency. Operating from a 1-V supply, the PA achieves a peak efficiency of 44% without any RF process options. This is comparable to that of state-of-the-art CMOS switching PAs despite using a much simpler output matching network. View full abstract»

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  • A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs

    Publication Year: 2012 , Page(s): 1123 - 1130
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2054 KB) |  | HTML iconHTML  

    A DCO is realized in 0.13 μm CMOS using 4 cores for a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for an all digital D/PLL CDR circuit. The DCO is novel in that it can track more than a 130 degree C temperature variation while the CDR maintains an error free lock to data. Each core is directly coupled to a div/2 to produce I/Q signals that a 4:1 MUX combines into a single set of 2.8 to 5.8 GHz quadrature outputs to drive the sine interpolator of the CDR. Locked to maximum data rms jitter, integrated from 1 kHz to 1 GHz is 299 fs @ 9.953 Gb/s (Sonet OC-192) from a DCO phase noise of -116 dBc/Hz at 1 MHz offset. The KDCO gain is 190 ppm/bit with less than 2:1 variation over the full bandwidth. The combined DCO, divide by 2 and MUX current is 14 mA to 37 mA on a 1.2 V regulated supply at 25°C. View full abstract»

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  • A Compact and Low Power 5–10 GHz Quadrature Local Oscillator for Cognitive Radio Applications

    Publication Year: 2012 , Page(s): 1131 - 1140
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1719 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of a compact and low power quadrature local oscillator (LO) for creating 13.3-20 GHz signal initially from a differentially tuned LC-VCO and then converting it to the desired 5-10 GHz with continuous frequency coverage. To accomplish such purpose, a 4-stage differential injection-locked ring oscillator (ILRO) is used subsequently to the latch-based divider to generate quadrature output phases without restricting 50% duty cycle from input signals as those of conventional divide-by-2 approaches. When implemented in a 65 nm general purpose CMOS IC technology, the integrated quadrature-phased LO consumes 22 mA of current at a 1 V supply and is able to exhibit the worst-case phase noise of -104 dBc/Hz at 1 MHz offset across the entire 5-10 GHz band for intended cognitive radio applications. View full abstract»

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  • A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass \Sigma \Delta ADC in 0.13 \mu m CMOS

    Publication Year: 2012 , Page(s): 1141 - 1153
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4251 KB) |  | HTML iconHTML  

    A reconfigurable bandpass continuous-time ΣΔ RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 μm CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is - 74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz. View full abstract»

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  • The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator

    Publication Year: 2012 , Page(s): 1154 - 1164
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2460 KB) |  | HTML iconHTML  

    An improved architecture of polar transmitter (TX) is presented. The proposed architecture is digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma ΔΣ modulator for envelop modulation, and a H-bridge class-D power amplifier (PA) for differential signaling. The ΔΣ modulator is clocked using the phase modulated RF carrier to ensure phase synchronization between the amplitude and phase path, and to guarantee the PA is switching at zero crossings of the output current. An on-chip pre-filter is used to reduce the parasitic capacitance from packages at the switch stage output. The high over sampling ratio of the ΔΣ modulator move quantization noise far away from the carrier frequency, ensuring good in-band performance and relax filter requirements. The on-chip filter also acts as impedance matching and differential to single-ended conversion. The measured digital transmitter consumes 58 mW from a 1-V supply at 6.8 dBm output power. View full abstract»

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  • A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX

    Publication Year: 2012 , Page(s): 1165 - 1174
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2490 KB) |  | HTML iconHTML  

    A wideband digital RF receiver front-end employing a discrete-time (DT) filter is presented for application to m-WiMAX (WiBro). By employing a sampling mixer and a DT filter, the receiver operates in the charge domain. In addition to the flexibility of the DT filter, the new non-decimation finite impulse response (NDF) filter can be cascaded to a conventional finite impulse response (FIR) filter without the decimation effect. Thus, we can easily increase the order of the sincn function-type filtering response and the signal processing bandwidth. The FIR filter is also modified to reduce the noise and the number of required clock signal. Because of the new filter configuration, clock signals can be shared by the FIR filter and NDF filter and the clock generator circuit can be simplified. The designed receiver front-end is implemented using an IBM 0.13-μm RF CMOS process. The fabricated chip satisfies the m-WiMAX specification of an 8.75 MHz channel bandwidth and the total system current dissipation is 26.63 mA from a 1.5-V supply voltage. View full abstract»

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  • Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology

    Publication Year: 2012 , Page(s): 1175 - 1184
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2581 KB) |  | HTML iconHTML  

    This paper presents a chipset aiming at high resolution imaging systems for real-time people screening applications operating near the W-band. The frequency of operation ranges from 70 GHz to 82 GHz for optimal image resolution and depth of focus. The frequency generation for both receiver and transmitter chips consists of a mixer based frequency quadrupler with an input amplifier requiring -20 dBm of input power. The receiver RFIC contains 4 channels including LO generation and distribution. The measured receiver conversion gain is 23 dB with a SSB NF around 10 dB over a wide frequency range from 70 GHz up to 82 GHz. The transmitter RFIC includes LO generation, distribution and 4 output amplifiers with an output power of more than 0 dBm in a frequency range from 70 GHz to 82 GHz. Both ICs are supplied from a single 3.3 V supply voltage and the power consumption is 180 mW/channel for the receiver and 145 mW/channel for the transmitter. View full abstract»

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  • A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications

    Publication Year: 2012 , Page(s): 1185 - 1198
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2029 KB) |  | HTML iconHTML  

    An improved envelope amplifier architecture for envelope tracking RF power amplifiers is presented, consisting of two switching amplifiers and one linear amplifier. The first switching amplifier and the linear amplifier provide wideband and high-efficiency operation, while the second switching amplifier provides a reduced bandwidth variable supply to the linear amplifier to further reduce power loss. The first switching amplifier and the linear amplifier are fabricated together in a 150 nm CMOS process, while the second switching amplifier is external. Measurements show a maximum average efficiency of 82% for a 10 MHz LTE signal with a 6 dB PAPR at 29.7 dBm output power and an SFDR of 63 dBc for a single tone of 5 MHz driving an 8 Ω load. View full abstract»

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  • A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile

    Publication Year: 2012 , Page(s): 1199 - 1208
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2563 KB) |  | HTML iconHTML  

    A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH ΔΣ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of ±0.5% to 3.5% in steps of 0.5% and three modulation frequencies of fm, 2 fm and 3 fm. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm2 in a 0.13-μm CMOS process and consuming 23.72 mW at 3.5 GHz. View full abstract»

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  • 32.9 nV/rt Hz {-} 60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC

    Publication Year: 2012 , Page(s): 1209 - 1220
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3191 KB) |  | HTML iconHTML  

    The dual-band recording of the local-field potential (LFP, 0.1-200 Hz) and the spike potential (SP, 200 Hz-10 kHz) is important for physiological studies at the cellular level. Recent study shows that the LFP signal plays important roles in modulating many profound cellular mechanisms. Although various bio-signal acquisition circuits have been reported over the years, few designs are applicable to capture both LFP and SP signals. To record both signals accurately, acquisition circuits need low noise and good linearity in both bands. In this paper, we report the design of a dual-band acquisition IC for microelectrode array (MEA) recording. The novel design uses a continuous-time (CT) front-end with chopping to suppress the noise in the LFP band, and a discrete-time (DT) back-end to achieve good linearity. The acquisition channel is fully differential, which leads to a high common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) without the 50 Hz injection. The design interfaces the microelectrode with a transistor gate, which has high input impedance. A prototype monolithic acquisition IC is fabricated in a 0.35 μm CMOS process. It includes 16 channels and an 11 bit successive-approximation (SAR) analog-to-digital converter (ADC). Every channel acquires cellular signals up to 20 mVpp with 32.9 nV/Hz0.5 and <; 0.1% nonlinearity. The good linearity effectively prevents the aliasing and mixing between the two bands. For LFP signal, the recording noise is 0.9 μVrms. For SP signal, the recording noise is 3.3 μVrms. The new design has high input impedance (320 M Ω@1 kHz), high CMRR ( >; 110 dB) and PSRR ( >; 110 dB). The noise-efficiency factor (NEF) of the acquisition channel is 7.6. The IC is experimented to record the field potential from cultured rat cardiomyocytes in-vitro. Overall, the new MEA acquisition channel achieves the state-of-art performance. View full abstract»

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  • A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 \mu m CMOS

    Publication Year: 2012 , Page(s): 1221 - 1231
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2945 KB) |  | HTML iconHTML  

    A 1.5 V low-power stereo audio codec in 0.13 μm CMOS is described. The microphone path includes a programmable gain stage with an enhanced transconductance cell followed by a continuous-time ΣΔ ADC with capacitive feed-forward and capacitive direct feedback. The speaker path employs a 1 mA Class-AB speaker amplifier with an improved quiescent current control circuit that delivers 30 mW to a 32 Ω speaker. The audio input and output paths achieve 92 and 98 dB dynamic range, respectively, with 6.5 mA total quiescent current. View full abstract»

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  • A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

    Publication Year: 2012 , Page(s): 1232 - 1241
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2040 KB) |  | HTML iconHTML  

    This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision. View full abstract»

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  • A 0.1–0.3 V 40–123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters

    Publication Year: 2012 , Page(s): 1242 - 1251
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3545 KB) |  | HTML iconHTML  

    This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3 V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -VDD to 2VDD swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V VDD. View full abstract»

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  • Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and {\rm V}_{\rm TH} -Tuned Oscillator With Fixed Charge Programming

    Publication Year: 2012 , Page(s): 1252 - 1260
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2085 KB) |  | HTML iconHTML  

    This paper presents a 95 mV startup-voltage step-up DC-DC converter for energy harvesting applications. The capacitor pass-on scheme enables operation of the system from an input voltage of 95 mV without using additional off-chip components. To compensate for the die-to-die process variation, post-fabrication threshold voltage (VTH) trimming is applied to reduce the minimum operating voltage (VDDMIN) of the oscillator. Experimental results demonstrate the 34% VDDMIN reduction of the oscillator by post-fabrication VTH trimming. The proposed step-up converter achieves the lowest startup voltage in standard CMOS without using a mechanical switch or large transformer. View full abstract»

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  • 2012 Radio Frequency Integrated Circuits Symposium

    Publication Year: 2012 , Page(s): 1261
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    Freely Available from IEEE
  • IEEE Asian Solid-State Circuits Conference

    Publication Year: 2012 , Page(s): 1262
    Save to Project icon | Request Permissions | PDF file iconPDF (904 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan