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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 4 • Date April 2012

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Displaying Results 1 - 19 of 19
  • Table of contents

    Page(s): C1 - 1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • Universal Principles for Ultra Low Power and Energy Efficient Design

    Page(s): 193 - 198
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (127 KB) |  | HTML iconHTML  

    Information is represented by the states of physical devices. It costs energy to transform or maintain the states of these physical devices. Thus, energy and information are deeply linked. This deep link allows the articulation of ten information-based principles for ultra low power design that apply to biology or electronics, to analog or digital systems, and to electrical or nonelectrical systems, at small or large scales. In this tutorial brief, we review these key principles along with examples of how they have been applied in practical electronic systems. View full abstract»

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  • Integration of Current-Reused VCO and Frequency Tripler for 24-GHz Low-Power Phase-Locked Loop Applications

    Page(s): 199 - 203
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (931 KB) |  | HTML iconHTML  

    This brief presents the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm × 0.8 mm is implemented in a 0.18-μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are -113.76 and -105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is -187.2 dBc/Hz. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. View full abstract»

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  • A 1.5-V Current Mirror Double-Balanced Mixer With 10-dBm IIP3 and 9.5-dB Conversion Gain

    Page(s): 204 - 208
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB) |  | HTML iconHTML  

    This brief presents the design of a double-balanced mixer for linearity-stringent communication systems. The pro- posed mixer is based on a current-mirror structure embedded with a switching pair. By utilizing the linear duplication characteristic of current mirrors, an improved linearity is achieved. The mixer is designed and fabricated in 0.18-μm 1P6M radio-frequency CMOS process, operating in the frequency band from 0.5 to 3 GHz. Measurement results indicate a peak conversion gain of 9.5 dB, a high input 3rd order intercept point (IIP3) of 10 dBm and a moderate noise figure (NF) of 16.5 dB. In addition, due to the folded structure, the mixer can be applicable in low-supply-voltage applications. The whole mixer has a compact die area of 0.1 mm2, and the power dissipation is 5.4 mW under 1.5-V supply voltage. View full abstract»

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  • A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor

    Page(s): 209 - 213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB) |  | HTML iconHTML  

    We demonstrate a novel adaptive look-ahead decision feedback equalizer (LADFE) that uses the measured eye diagram for equalization adaptation and verification. The eye diagram is obtained with a new type of eye-opening monitor (EOM), which measures the magnitude of the received signals having different data patterns and, using this, estimates intersymbol interference and determines the amount of adaptation needed for the LADFE. A 10-Gb/s adaptive two-tap LADFE with an EOM is fabricated in 90-nm CMOS technology. The eye diagrams for equalized signals are successfully obtained, and adaptation of the LADFE is achieved for PCB channels up to 40 cm. The LADFE core occupies and consumes 11 mW at 1.2-V supply voltage. View full abstract»

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  • A 2G/3G Cellular Analog Baseband Based on a Filtering ADC

    Page(s): 214 - 218
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entire baseband analog section of a Global System for Mobile Communications-Universal Mobile Telecommunications System (GSM-UMTS) reconfigurable receiver. View full abstract»

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  • RF/DSP Codesign Methodology of Enhanced Doherty Amplifiers

    Page(s): 219 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (761 KB) |  | HTML iconHTML  

    In this brief, a mixed radio frequency/digital signal processing (DSP) codesign approach is proposed to enhance the performance of Doherty power amplifiers (PAs). For the hardware optimization, a load-pull-based design methodology is proposed to determine the optimal matching elements of the main amplifier for enhanced efficiency at back-off. Subsequently, DSP control of the baseband input signal is used to efficiently distribute the drive power between the main and auxiliary amplifiers in order to enhance the efficiency at high power levels and also to improve the linearity. Precisely, the input power is evenly distributed between the two amplifiers at the back-off region and then unequally split with more drive into the auxiliary amplifier once the latter turns on. This allows for improving the load modulation behavior of the Doherty PA and flattening its gain response, which yield enhanced efficiency and improved linearity. For the experimental validation, the proposed codesign approach is applied to implement a dual-input Doherty PA based on a 10-W gallium nitride (GaN) device. Measurement results with wideband code division multiple access demonstrated improvements of up to 5% in average drain efficiency and up to 3 dB in adjacent channel leakage ratio. View full abstract»

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  • A 2.45-GHz + 20-dBm Fast Switching Class-E Power Amplifier With 43% PAE and a 18-dB-Wide Power Range in 0.18- \mu \hbox {m} CMOS

    Page(s): 224 - 228
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    In this brief, the losses in Class-E power amplifiers (PAs) with finite dc-feed inductance are analyzed. This analysis results in practical analytical expressions, which significantly simplify the design and optimization of Class-E PAs. To demonstrate their applicability, the design of a state-of-the-art 2.45-GHz differential cascode Class-E PA in 0.18- CMOS with on-chip dc-feed inductor is presented. By the proposed combination of a dynamic supply voltage and a dynamic cascode bias voltage, high drain efficiency is achieved over a wide power control range, covering from 2.2 up to 20 dBm. At 20 dBm, a power-added efficiency as high as 43.6% was measured. Additionally, fast envelope switching is obtained by adding a single switch to the common-gate nodes of both the Class-E stage and the second driver stage. Measurements show a rise time of merely 2.5 ns and a 73-dB isolation between the on- and off-states. These figures enable ranging applications with submeter accuracy. View full abstract»

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  • Converting a Three-Stage Pseudoclass-AB Amplifier to a True-Class-AB Amplifier

    Page(s): 229 - 233
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (563 KB) |  | HTML iconHTML  

    We convert a low-voltage low-transistor-count wide-swing multistage pseudoclass-AB amplifier proposed by Mita et al. to a true-class-AB amplifier. The conversion is made possible using gate-drain feedback to combine two inverting common- source amplifiers to form a single noninverting stage. Both the pseudoclassand true-class-AB amplifiers were fabricated in a 0.5-μm CMOS 2P3M process. They are designed to operate from ±1.25-V supplies at a nominal quiescent current of 175 μA and a minimum phase margin of 45° when driving capacitive loads from 1 to 200 pF and resistive loads from 500 Ω to 1 MΩ. The total com- pensation capacitance of the proposed class-AB amplifier is 12 pF, which is 50% less than the pseudoclass-AB amplifier. The simu- lated unity-gain frequency of the class-AB amplifier is 4.9 MHz at a load of 25 pF||1kΩ, which is 88% higher than that of the pseudoclass-AB amplifier. Experimental measurements show that the proposed amplifier has a maximum total bias current of 175 μA, as compared with 1.05 mA for the pseudoclass-AB am- plifier. Measured slew rates of the proposed amplifier are 2.7 and 3.3 V/μs, twice as much as those of its pseudoclass-AB counterpart. View full abstract»

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  • A Low-Power and High-Precision Programmable Analog Filter Bank

    Page(s): 234 - 238
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (451 KB) |  | HTML iconHTML  

    Analog filter banks befit remote audio- and vibration-sensing applications, which require frequency analysis to be performed with low-power consumption and with moderate-to-high precision. The precision of a filter bank depends on both the signal-path precision (i.e., dynamic range) and also the parameter precision (e.g., accuracy of the center frequencies). This brief presents a new bandpass filter for audio-frequency filter banks and provides a procedure for designing this filter. The filter is used in a 16-channel filter bank which has been fabricated in a 0.35- CMOS process. This filter bank has a dynamic range exceeding 62 dB and consumes only 63.6 when biased for speech frequencies. The filter bank's parameters are set via floating-gate current sources. This brief shows how to use these floating gates to obtain a versatile filter bank that can be precisely reprogrammed to arbitrary filter spacings and frequency weightings, with a parameter accuracy exceeding 99%. View full abstract»

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  • Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering

    Page(s): 239 - 243
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain. View full abstract»

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  • MRC-Based RNS Reverse Converters for the Four-Moduli Sets {2^{n} + 1, 2^{n} - 1, 2^{n}, 2^{2n + 1} - 1} and  {2^{n} + 1, 2^{n} - 1, 2^{2n}, 2^{2n + 1} - 1}

    Page(s): 244 - 248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    The moduli set {2n + 1,2n - 1,2n, 22n+1 -1} has been recently proposed for supporting residue number systems with dynamic ranges of 5n bits. In this brief, we suggest modifying this moduli set to {2n + 1,2n - 1,2n, 22n+1 -1},in order to enlarge the dynamic range to 6n bits. We propose a method that unifies the design of efficient reverse converters for the original and the modified moduli sets. A unified architecture was derived to design individual reverse converters for each moduli set or to achieve a single configurable reverse converter. Experimental results show that the delay of the converters designed with the proposed method and implemented on a 65-nm CMOS integrated circuit is improved by 12% on average. Moreover, the product of the area with the square of the delay is improved up to 25% and 21%, when compared to the related state of the art and values of n between 6 and 32, for dynamic ranges of 5n and 6n bits, respectively. View full abstract»

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  • Design Techniques for NBTI-Tolerant Power-Gating Architectures

    Page(s): 249 - 253
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these types of devices, an NBTI-induced current capability degradation translates into a larger -drop effect on the virtual- rail, which unconditionally affects the performance and, thus, the reliability of all power-gated cells. In this brief, we address the problem of designing NBTI-tolerant power-gating architectures. We propose a set of efficient NBTI-aware circuit design solutions, including both static and dynamic strategies, that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads. Experimental results prove the effectiveness of such techniques when applied to a suite of benchmarks mapped onto a 45-nm industrial CMOS technology library. In particular, we prove that it is possible to achieve more than ten times of lifetime extension with respect to a traditional power-gating approach. View full abstract»

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  • ISCAS 2013

    Page(s): 254
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  • Special issue on ultra low voltage vlsicircuits and systems

    Page(s): 255
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

    Page(s): 256
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope