# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 19 of 19

Publication Year: 2012, Page(s):C1 - 1
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2012, Page(s): C2
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• ### Universal Principles for Ultra Low Power and Energy Efficient Design

Publication Year: 2012, Page(s):193 - 198
Cited by:  Papers (12)
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Information is represented by the states of physical devices. It costs energy to transform or maintain the states of these physical devices. Thus, energy and information are deeply linked. This deep link allows the articulation of ten information-based principles for ultra low power design that apply to biology or electronics, to analog or digital systems, and to electrical or nonelectrical system... View full abstract»

• ### Integration of Current-Reused VCO and Frequency Tripler for 24-GHz Low-Power Phase-Locked Loop Applications

Publication Year: 2012, Page(s):199 - 203
Cited by:  Papers (18)
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This brief presents the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm × 0.8 mm is implemented in a 0.18-μm CMOS process. As the tu... View full abstract»

• ### A 1.5-V Current Mirror Double-Balanced Mixer With 10-dBm IIP3 and 9.5-dB Conversion Gain

Publication Year: 2012, Page(s):204 - 208
Cited by:  Papers (13)
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This brief presents the design of a double-balanced mixer for linearity-stringent communication systems. The pro- posed mixer is based on a current-mirror structure embedded with a switching pair. By utilizing the linear duplication characteristic of current mirrors, an improved linearity is achieved. The mixer is designed and fabricated in 0.18-μm 1P6M radio-frequency CMOS process, operati... View full abstract»

• ### A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor

Publication Year: 2012, Page(s):209 - 213
Cited by:  Papers (6)  |  Patents (1)
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We demonstrate a novel adaptive look-ahead decision feedback equalizer (LADFE) that uses the measured eye diagram for equalization adaptation and verification. The eye diagram is obtained with a new type of eye-opening monitor (EOM), which measures the magnitude of the received signals having different data patterns and, using this, estimates intersymbol interference and determines the amount of a... View full abstract»

• ### A 2G/3G Cellular Analog Baseband Based on a Filtering ADC

Publication Year: 2012, Page(s):214 - 218
Cited by:  Papers (8)  |  Patents (3)
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A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entir... View full abstract»

• ### RF/DSP Codesign Methodology of Enhanced Doherty Amplifiers

Publication Year: 2012, Page(s):219 - 223
Cited by:  Papers (10)
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In this brief, a mixed radio frequency/digital signal processing (DSP) codesign approach is proposed to enhance the performance of Doherty power amplifiers (PAs). For the hardware optimization, a load-pull-based design methodology is proposed to determine the optimal matching elements of the main amplifier for enhanced efficiency at back-off. Subsequently, DSP control of the baseband input signal ... View full abstract»

• ### A 2.45-GHz $+$20-dBm Fast Switching Class-E Power Amplifier With 43% PAE and a 18-dB-Wide Power Range in 0.18-$mu hbox{m}$ CMOS

Publication Year: 2012, Page(s):224 - 228
Cited by:  Papers (7)
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In this brief, the losses in Class-E power amplifiers (PAs) with finite dc-feed inductance are analyzed. This analysis results in practical analytical expressions, which significantly simplify the design and optimization of Class-E PAs. To demonstrate their applicability, the design of a state-of-the-art 2.45-GHz differential cascode Class-E PA in 0.18- CMOS with on-chip dc-feed inductor is presen... View full abstract»

• ### Converting a Three-Stage Pseudoclass-AB Amplifier to a True-Class-AB Amplifier

Publication Year: 2012, Page(s):229 - 233
Cited by:  Papers (6)
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We convert a low-voltage low-transistor-count wide-swing multistage pseudoclass-AB amplifier proposed by Mita et al. to a true-class-AB amplifier. The conversion is made possible using gate-drain feedback to combine two inverting common- source amplifiers to form a single noninverting stage. Both the pseudoclassand true-class-AB amplifiers were fabricated in a 0.5-μm CMOS 2P3M process. They... View full abstract»

• ### A Low-Power and High-Precision Programmable Analog Filter Bank

Publication Year: 2012, Page(s):234 - 238
Cited by:  Papers (10)
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Analog filter banks befit remote audio- and vibration-sensing applications, which require frequency analysis to be performed with low-power consumption and with moderate-to-high precision. The precision of a filter bank depends on both the signal-path precision (i.e., dynamic range) and also the parameter precision (e.g., accuracy of the center frequencies). This brief presents a new bandpass filt... View full abstract»

• ### Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering

Publication Year: 2012, Page(s):239 - 243
Cited by:  Papers (14)
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A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modificatio... View full abstract»

• ### MRC-Based RNS Reverse Converters for the Four-Moduli Sets ${2^{n} + 1, 2^{n} - 1, 2^{n}, 2^{2n + 1} - 1}$ and ${2^{n} + 1, 2^{n} - 1, 2^{2n}, 2^{2n + 1} - 1}$

Publication Year: 2012, Page(s):244 - 248
Cited by:  Papers (27)
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The moduli set {2n + 1,2n - 1,2n, 22n+1 -1} has been recently proposed for supporting residue number systems with dynamic ranges of 5n bits. In this brief, we suggest modifying this moduli set to {2n + 1,2n - 1,2n, 22n+1 -1},in order to enlarge the dynamic range to 6n bits. We propose a method that unifies the ... View full abstract»

• ### Design Techniques for NBTI-Tolerant Power-Gating Architectures

Publication Year: 2012, Page(s):249 - 253
Cited by:  Papers (8)
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While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these... View full abstract»

• ### ISCAS 2013

Publication Year: 2012, Page(s): 254
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• ### Special issue on ultra low voltage vlsicircuits and systems

Publication Year: 2012, Page(s): 255
| PDF (310 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2012, Page(s): 256
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• ### IEEE Circuits and Systems Society Information

Publication Year: 2012, Page(s): C3
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• ### [Blank page]

Publication Year: 2012, Page(s): C4
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## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org