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Solid-State Circuits, IEEE Journal of

Issue 4 • Date April 2012

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Displaying Results 1 - 25 of 32
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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  • Table of contents

    Page(s): 793 - 794
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  • Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits

    Page(s): 795 - 796
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  • A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications

    Page(s): 797 - 809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2504 KB) |  | HTML iconHTML  

    A 1920 × 1080 160° object viewpoint recognition system-on-chip (SoC) is presented in this paper. The SoC design is dedicated to wearable vision applications, and we address several crucial issues including the low recognition accuracy due to the use of low resolution images and dramatic changes in object viewpoints, and the high power consumption caused by the complex computations in existing computer vision object recognition systems. The human-centered design (HCD) mechanism is proposed in order to maintain a high recognition rate in difficult situations. To overcome the degradation of accuracy when dramatic changes to the object viewpoint occur, the object viewpoint prediction (OVP) engine in the HCD provides 160° object viewpoint in- variance by synthesizing various object poses from predicted object viewpoints. To achieve low power consumption, the visual vocabulary processor (VVP), which is based on bag-of-words (BoW) matching algorithm, is used to advance the matching stage from the feature-level to the object-level and results in a 97% reduction in the required memory bandwidth compared to previous recognition systems. Moreover, the matching efficiency of the VVP enables the system to support real-time full HD (1920 × 1080) processing, thereby improving the recognition rate for detecting a traffic light at a distance of 50 m to 95% compared to the 29% recognition rate for VGA (640 × 480) processing. The real-time 1920 × 1080 visual recognition chip is realized on a 6.38 mm2 die with 65 nm CMOS technology. It achieves an average recognition rate of 94%, a power efficiency of 1.18 TOPS/W, and an area efficiency of 25.9 GOPS/mm2 while only dissipating 52 mW at 1.0 V. View full abstract»

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  • Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs

    Page(s): 810 - 816
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1931 KB) |  | HTML iconHTML  

    The isolation techniques against substrate noise coupling utilizing through silicon via (TSV) process are described. The trench shape TSV encloses the RF circuit on a SoC chip to improve the isolation between digital circuits and the RF circuits without constraints of on-chip interconnect above first metal as the TSV is connected to the grounded 1st metal from the back side of the substrate. The analysis with simplified model is proposed to show the effect of the proposed isolation techniques. Mesh circuit model is applied to simulate the noise distribution in detail. Various test patterns are fabricated on a CMOS silicon substrate with resistivity of 10 Ωcm. The measurement pattern of H-shaped TSV confirms about 30 dB and 40 dB improvement at 100 MHz and 1 GHz respectively, which is much better than conventional isolation techniques such as guard ring, Deep N-well and DTI. The combinational pattern with TSV, DTI and high resistive layer shows 60 dB improvement of the isolation. Proposed isolation techniques are useful for substrate noise coupling of future RF/mixed-signal SoCs. View full abstract»

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  • A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder

    Page(s): 817 - 831
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    This paper presents a (491,3,6) time-varying low-density parity check convolutional code (LDPC-CC) decoder chip. This work combines the algorithm level, node level, and bit level optimizations to achieve over 2 Gb/s throughput with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activation scheduling with concealing channel values, which can not only achieve twice faster decoding convergence speed than log-belief propagation (log-BP) algorithm, but also reduce the 17% message storage capacity. The node level optimization duplicates the check node units and variable node units and unfolds the message storage first-in-first-outs (FIFOs) so that the throughput becomes twelve multiplying with clock frequency. In the meantime, the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has been fabricated in 90 nm CMOS technology with core area of 2.37 × 1.14 mm2. Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit/proc. Depending on the operation mode, power can be scaled down to 90.2 mW while maintaining 1.58 Gb/s at 0.8 V supply. View full abstract»

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  • A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

    Page(s): 832 - 840
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    AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%. View full abstract»

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  • A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a \Delta \Sigma -Modulator Controller With a Scalable Sampling Frequency

    Page(s): 841 - 851
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    This paper presents a spurious-free switching buck converter with enhanced light-load efficiency for use in noise-sensitive portable electronics. The proposed switching buck converter achieves low output noise by using a delta-sigma-modulator (ΔΣ) controller. Its light-load efficiency is enhanced by: 1) scaling the switching frequency of the buck converter (i.e., the sampling frequency of its ΔΣ-modulator controller) with the load current; 2) switching its operation from continuous conduction mode (CCM) to discontinuous conduction mode (DCM) at light loads; and 3) using a new low-power current-sensing circuit. The ΔΣ modulator is designed with an input-feedforward architecture, which enables the switching frequency of the controller to be scaled without disturbing the stability of the feedback loop of the buck converter, and also reduces the controller quiescent current. The proposed switching buck converter was fabricated in 0.13-μm digital CMOS. Measurements results demonstrate that this buck converter achieves a spurious-free output with a noise floor below -60 dBm and voltage ripples below 70 mV over its full loading range (2 mA to 800 mA). Furthermore, it achieves a power efficiency higher than 70% over this entire range, with a peak efficiency of 95.1%. View full abstract»

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  • A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With \alpha -Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control

    Page(s): 852 - 862
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    A battery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed α-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-μm CMOS process with a die area of 0.39 mm2. Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications. View full abstract»

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  • Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage

    Page(s): 863 - 874
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    A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an asynchronous comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from a slow outer feedback loop. The feedback through the charge pumps also ensures balanced load sharing among the UREGs. Two techniques are introduced to reduce the output ripple generated by switching the pMOS passgate on and off: hybrid fast/slow passgate control (in which the DC portion of the load current is supplied by a parallel output device with slew-rate-limited gate drive) and pMOS strength calibration (which adjusts the active width of the passgate to compensate for PVT variations). The distributed regulator system is integrated into a DDR3 I/O core and supplies power to CMOS delay lines used for clock-to-data deskewing. Each of the eight UREGs is sized to provide up to 5.3 mA of load current and occupies an area of 55 × 60 μm2. The measured DC load regulation is better than 10 mV down to an 85-mV dropout voltage. Jitter readings of the CMOS delay lines indicate output noise close to 28 mVpp. View full abstract»

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  • A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping \Delta \Sigma TDC

    Page(s): 875 - 883
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    This paper presents a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to a fractional-N digital PLL. With a simple structure of single-delay-stage Δ modulator followed by a charge pump based Σ modulator, a wide range of TDC input is converted to ΔΣ modulated single bit stream without loss of signal information. The ΔΣ architecture of TDC effectively improves the conversion performance of linearity and resolution while handling a large input range due to the operation of the dual-modulus divider. In addition, with a downscaling of the amount of the single delay in Δ modulator, the signal and noise transfer characteristics of TDC can be profiled to suppress the out-band noises at the input to the loop filter, resulting in easy filtering without any extra noise cancelling scheme. The DPLL is fabricated with a 0.13 μm CMOS technology. With a loop bandwidth of 1 MHz, DPLL shows an in-band phase noise of - 107 dBc/Hz at 500 kHz offset and an out-of-band phase noise of -118.5 dBc/Hz at 3 MHz offset. The TDC consumes 1 mA. View full abstract»

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  • An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

    Page(s): 884 - 896
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    A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 μm-pitch μC4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg μ C4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 μm and 22 μm. 8 × 10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8 × 9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit. View full abstract»

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  • A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

    Page(s): 897 - 910
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    A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is shown that the transceiver power and the effect of high-frequency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE). On the circuit level, the receiver uses a switched-capacitor (SC) approach for the implementation of an 8-tap decision-feedback equalizer (DFE). The SC-DFE improves the timing margin relative to previous DFE implementations with current feedback, and leads to a digital-style circuit implementation with compact layout. The receiver was measured at data rates up to 13.5 Gb/s, where error free operation was verified with a PRBS-31 sequence and a channel with 32 dB attenuation at Nyquist. With the clock generation circuits amortized over eight lanes, the receiver circuit consumes 2.6 mW/Gbps from a 1.1 V supply while running at 12.5 Gb/s. View full abstract»

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  • A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

    Page(s): 911 - 925
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    This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the × 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps. View full abstract»

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  • A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

    Page(s): 926 - 937
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    This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3" FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor intersymbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory. In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory. The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5 × energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation. View full abstract»

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  • Power Optimized ADC-Based Serial Link Receiver

    Page(s): 938 - 951
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3739 KB) |  | HTML iconHTML  

    Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital signal post-processing has drawn growing interest with technology scaling, but power consumption remains among the key issues for such digital receiver in high speed applications. This paper presents an ADC-based receiver that uses a low-gain analog and mixed-mode pre-equalizer in conjunction with non-uniform reference levels for the ADC. The combination compensates for both the frontend non-ideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. The receiver is fabricated in a 65 nm CMOS technology with 10 Gb/s data rate, and has 13 pJ/bit and 10.6 pJ/bit power efficiency for a 29 dB and a 23 dB loss channel respectively. View full abstract»

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  • A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS

    Page(s): 952 - 968
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    This paper presents a low-power mixed-signal adaptive 60 GHz baseband in 65 nm CMOS. The design integrates variable gain amplifiers, analog phase rotator, 40-coefficient I/Q decision feedback equalizers (DFEs), clock generation and data recovery circuits, and adaptation hardware. The baseband achieves 10 Gb/s operation with BER <; 10-12 while consuming 53 mW (adaptation on)/45 mW (adaptation off), of which the core signal processing circuits consume only 29 mW. View full abstract»

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  • Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

    Page(s): 969 - 980
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    This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with <;2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width according to on-site measurement results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates the need for additional margins related to BL voltage swing, which has conventionally been required to ensure adequate tolerances against simulation errors and inaccurate estimation of SA offset voltage. This opens up possibilities for a more aggressive approach to deal with WLP width instead of only ensuring the target BL voltage swing. View full abstract»

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  • A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

    Page(s): 981 - 989
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    A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed. View full abstract»

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  • RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass \Delta \Sigma Modulator and Polyphase Decimation Filter

    Page(s): 990 - 1002
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2643 KB) |  | HTML iconHTML  

    A fourth-order continuous-time RF bandpass ΔΣ ADC has been fabricated in 40 nm CMOS for fs/4 operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the fractional-N PLL with clock generation network, and the digital decimation filters and downconversion (DFD). The quantizers of the ADC are six times interleaved enabling a polyphase structure for the DFD and relaxing clock frequency requirements. This quantization scheme realizes a sampling rate of 8.88 GS/s which is the highest sampling speed for RF bandpass ΔΣ ADCs reported in standard CMOS to date enabling high oversampling ratios for RF digitization without compromising power-efficient implementation of the DFD. Measurements show that the ADC achieves a dynamic range of 48 dB in a band of 80 MHz with an IIP3 of 1 dBm. View full abstract»

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  • A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz {\rm f}_{\rm T} BiCMOS Process

    Page(s): 1003 - 1012
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    We present a complete signal generator with integrated digital-to-analog convertor (DAC) on a chip which can generate complex waveforms at up to 7.2 GSa/s with 14 bit resolution or at up to 12 GSa/s with 12 bit resolution. The 3 dB bandwidth is 4.4 GHz. The chip includes digital signal processing (DSP) logic for agile generation of wideband modulated RF signals (up to 480 MHz modulation bandwidth) as well as high fidelity chirp and continuous wave signals. There is also DSP for integral non-linearity error reduction and suppression of clock sub-harmonics. The DAC uses a segmented architecture with 4 unary most significant bits and an R/2R ladder for the 10 binary least significant bits. Distributed resampling is applied to all current sources to improve the dynamic performance. At 7.2 GSa/s it delivers at least 67 dB spurious free dynamic range (SFDR) across the whole Nyquist region and an SNR of 62 dB. It demonstrates - 157 dBc/Hz phase noise at 10 kHz offset from a 1 GHz carrier, 22 dB better than known synthesized signal generation instruments. The chip is built in a 165 GHz fT, 130 nm BiCMOS process and is packaged in a 780 ball BGA. View full abstract»

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  • A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm ^{2} and 500 mW in 40 nm Digital CMOS

    Page(s): 1013 - 1021
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    A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital converter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs with minimum channel length for key analog blocks. Moreover, in terms of the signal swing, the proposed reference extrapolation scheme offers a smooth transition between the multiplying digital-to-analog converter stages and the last flash stage. With these two techniques, the ADC achieves a SNR of 61 dB and a DNL of -0.5/+0.5 LSB, while consuming 500 mW at a 3 GS/s sampling rate and occupying an area of 0.4 mm2 in 40 nm CMOS process. View full abstract»

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  • A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

    Page(s): 1022 - 1030
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    This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm. View full abstract»

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  • CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography

    Page(s): 1031 - 1042
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3306 KB) |  | HTML iconHTML  

    This paper presents new image sensors with multi- bucket pixels that enable time-multiplexed exposure, an alter- native imaging approach. This approach deals nicely with scene motion, and greatly improves high dynamic range imaging, structured light illumination, motion corrected photography, etc. To implement an in-pixel memory or a bucket, the new image sensors incorporate the virtual phase CCD concept into a standard 4-transistor CMOS imager pixel. This design allows us to create a multi-bucket pixel which is compact, scalable, and supports true correlated double sampling to cancel kTC noise. Two image sensors with dual and quad-bucket pixels have been designed and fabricated. The dual-bucket sensor consists of a 640H × 576V array of 5.0 μm pixel in 0.11 μm CMOS technology while the quad-bucket sensor comprises 640H × 512V array of 5.6 μm pixel in 0.13 μm CMOS technology. Some computational photography applications were implemented using the two sensors to demonstrate their values in eliminating artifacts that currently plague computational photography. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan