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# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 55

Publication Year: 2012, Page(s):C1 - 874
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2012, Page(s): C2
| PDF (52 KB)
• ### The Peer Review Process and EDS Golden List of Reviewers

Publication Year: 2012, Page(s):875 - 877
| PDF (40 KB) | HTML
• ### Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs

Publication Year: 2012, Page(s):878 - 887
Cited by:  Papers (36)  |  Patents (1)
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We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ's critical swit... View full abstract»

• ### Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

Publication Year: 2012, Page(s):888 - 894
Cited by:  Papers (52)
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In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications, such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO... View full abstract»

• ### Characteristics of a 4H-SiC Pin Diode With Carbon Implantation/Thermal Oxidation

Publication Year: 2012, Page(s):895 - 901
Cited by:  Papers (15)
| | PDF (678 KB) | HTML

The forward voltage drops of pin diodes with the carbon implantation or thermal oxidation process using a drift layer of 120 μm thick are around 4.0 V and are lower than those with the standard process. The reverse recovery characteristics of pin diodes with the standard or carbon implantation process show almost the same tendency. In the reverse recovery characteristics at 250 °... View full abstract»

• ### Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors

Publication Year: 2012, Page(s):902 - 908
Cited by:  Papers (68)
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A scaling theory of double-gate interband tunnel field-effect transistors (TFETs) using a physics-based 2-D analytical model is presented. Ignoring the mobile charge in the channel, the electrostatic potential profile and electric field are analytically solved, and the current is calculated by integrating the band-to-band tunneling generation rate over the volume of the device. The analytical mode... View full abstract»

• ### 19% Efficient Thin-Film Crystalline Silicon Solar Cells From Layer Transfer Using Porous Silicon: A Loss Analysis by Means of Three-Dimensional Simulations

Publication Year: 2012, Page(s):909 - 917
Cited by:  Papers (6)
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We present a study about loss analysis in both-sides-contacted silicon solar cells from a porous silicon (PSI) layer transfer process. Experimental results achieved by a variation of the rear-side contact geometry are characterized by different techniques such as electroluminescence and quantum efficiency measurements and reproduced by 3-D simulations using Sentaurus Device. Since such a device si... View full abstract»

• ### Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation

Publication Year: 2012, Page(s):918 - 923
Cited by:  Papers (6)
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Single-electron transistor (SET) circuits can be stacked above the CMOS platform to achieve functional and heterogeneous 3-D integration of nanoelectronic devices. For SET-CMOS hybridization, CMOS technology is essential for I/O, signal restoration, and maintaining compatibility with established technology. In spite of the SET's unparalleled advantages, its low current drive and output voltage whe... View full abstract»

• ### RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates

Publication Year: 2012, Page(s):924 - 932
Cited by:  Papers (33)  |  Patents (1)
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In this paper, the nonlinear behavior of coplanar waveguide (CPW) transmission lines fabricated on Si and high-resistivity (HR) Si substrates is thoroughly investigated. Simulations and experimental characterization of 50- Ω CPW lines are analyzed under small- and large-signal operation at 900 MHz for a wide variety of Si substrates with nominal resistivities from 10 Ω-cm up to value... View full abstract»

• ### Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- $k$ Control Dielectrics

Publication Year: 2012, Page(s):933 - 940
Cited by:  Papers (11)
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In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential us... View full abstract»

• ### Physical Model of the Junctionless UTB SOI-FET

Publication Year: 2012, Page(s):941 - 948
Cited by:  Papers (37)
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In this paper, we model the electrical properties of a junctionless (JL) ultrathin-body silicon-on-insulator field-effect transistor (SOI-FET), which has been proposed as a possible alternative to the junction-based SOI-FET. The model is based on improved depletion approximation, which provides a very accurate solution of Poisson's equation and allows for the computation of the substrate, as well ... View full abstract»

• ### Temperature-Oriented Mobility Measurement and Simulation to Assess Surface Roughness in Ultrathin-Gate-Oxide ( $sim$1 nm) nMOSFETs and Its TEM Evidence

Publication Year: 2012, Page(s):949 - 955
Cited by:  Papers (13)
| | PDF (1417 KB) | HTML

On a 1.27-nm gate-oxide nMOSFET, we make a comprehensive study of SiO2/Si interface roughness by combining temperature-dependent electron mobility measurement, sophisticated mobility simulation, and high-resolution transmission electron microscopy (TEM) measurement. Mobility measurement and simulation adequately extract the correlation length λ and roughness rms height Δ o... View full abstract»

• ### Switching Behavior in Rare-Earth Films Fabricated in Full Room Temperature

Publication Year: 2012, Page(s):956 - 961
Cited by:  Papers (4)
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In this paper, we investigated the forming-free resistive-switching (RS) behavior in the Ru/REOx/TaN ( RE = Ce, Pr, Sm, and Eu) memory device using CeOx, PrOx, SmOx, and EuOx thin films fabricated in a full-room-temperature process. The dominant conduction mechanism of Ru/REOx/TaN memory devices in the low-resistance state is ohmic ... View full abstract»

• ### Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device

Publication Year: 2012, Page(s):962 - 967
Cited by:  Papers (56)  |  Patents (1)
| | PDF (524 KB) | HTML

A distinctive approach for forming a lateral bipolar charge-plasma transistor (BCPT) is explored using 2-D simulations. Different metal work-function electrodes are used to induce n- and p-type charge-plasma layers on undoped silicon-on-insulator (SOI) to form the emitter, base, and collector regions of a lateral n-p-n transistor. Electrical characteristics of the proposed device are simulated and... View full abstract»

• ### A Large-Signal Graphene FET Model

Publication Year: 2012, Page(s):968 - 975
Cited by:  Papers (28)
| | PDF (937 KB) | HTML

We propose a semi-empirical graphene field-effect-transistor (G-FET) model for analysis and design of G-FET-based circuits. The model describes the current-voltage characteristic for a G-FET over a wide range of operating conditions. The gate bias dependence of the output power spectrum is studied and compared with the simulated values. Good agreement between the simulated and the experimental pow... View full abstract»

• ### Semiclassical Monte Carlo Analysis of Graphene FETs

Publication Year: 2012, Page(s):976 - 982
Cited by:  Papers (17)
| | PDF (528 KB) | HTML

We present a 3-D semiclassical Monte Carlo simulator for modeling transport in graphene metal-oxide-semiconductor field-effect transistors (MOSFETs). We have calibrated our material simulations by matching simulation results to experimental bulk velocity-field curves. We have included a full range of phonon-scattering mechanisms, intrinsic and oxide/extrinsic remote impurity charges, and carrier-c... View full abstract»

• ### An Efficient Nonlocal Hot Electron Model Accounting for Electron–Electron Scattering

Publication Year: 2012, Page(s):983 - 993
Cited by:  Papers (4)
| | PDF (1251 KB) | HTML

This paper presents a nonlocal model for channel hot electron injection in MOSFETs and nonvolatile memories, which includes a full-band description of optical phonon scattering rates and carrier group velocity. By virtue of its efficient formalism, this model can also include carrier-carrier scattering, which has a marked impact on gate current at low gate voltages. The model is compared against f... View full abstract»

• ### On the Interpretation of Ballistic Injection Velocity in Deeply Scaled MOSFETs

Publication Year: 2012, Page(s):994 - 1001
Cited by:  Papers (19)
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The ballistic injection velocity is examined in state-of-the-art Si extremely thin SOI MOSFETs using ballistic quantum simulations and a virtual source (VS) compact model. The results indicate that the device performs at around 50%-60% of its ballistic limit and that the ballistic injection velocity at the top of the potential barrier (ToB), as obtained by numerical simulation, can be significantl... View full abstract»

• ### A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Publication Year: 2012, Page(s):1002 - 1007
Cited by:  Papers (13)
| | PDF (497 KB) | HTML

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affec... View full abstract»

• ### A Compact Model of Quantum Electron Density at the Subthreshold Region for Double-Gate Junctionless Transistors

Publication Year: 2012, Page(s):1008 - 1012
Cited by:  Papers (21)
| | PDF (231 KB) | HTML

A compact model of quantum electron density at the subthreshold region is derived for junctionless (JL) double-gate (DG) FETs. The proposed quantum model is obtained under two different quantum confinement conditions. One is for a case of a thick channel and a heavily doped channel, where quantum confinement effects (QCEs) are modeled by a 1-D quantum harmonic oscillator. The other is for a case o... View full abstract»

• ### Are Interface State Generation and Positive Oxide Charge Trapping Under Negative-Bias Temperature Stressing Correlated or Coupled?

Publication Year: 2012, Page(s):1013 - 1022
Cited by:  Papers (13)
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Studies have suggested that interface state generation under negative-bias temperature (NBT) stress results in positive oxide charge trapping. The latter is ascribed to the trapping of hydrogen species, from Si-H bond dissociation, in the oxide bulk. In this paper, we present evidence from dynamic NBT instability showing no apparent relationship between the two degradation mechanisms. The level of... View full abstract»

• ### Effect of Band-to-Band Tunneling on Junctionless Transistors

Publication Year: 2012, Page(s):1023 - 1029
Cited by:  Papers (54)
| | PDF (1026 KB) | HTML

We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs). A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions. This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs. This BTBT leads to ... View full abstract»

• ### Impact Ionization Coefficients in 4H-SiC by Ultralow Excess Noise Measurement

Publication Year: 2012, Page(s):1030 - 1036
Cited by:  Papers (3)
| | PDF (646 KB) | HTML

Photomultiplication and excess noise measurements have been undertaken on two 4H-SiC avalanche photodiodes (APDs) using 244-nm light and 325-nm light. The structures are APDs with separate absorption and multiplication regions having multiplication regions of 2.74 and 0.58 μm , respectively. Pure injection conditions in the thicker device permit the measurement of pure-hole-initiated photom... View full abstract»

• ### Gate Capacitance Modeling and Diameter-Dependent Performance of Nanowire MOSFETs

Publication Year: 2012, Page(s):1037 - 1045
Cited by:  Papers (14)
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We investigated the diameter-dependent performance of Si and InAs nanowire metal-oxide-semiconductor field-effect transistors (NW MOSFETs) by developing a gate capacitance model. A nonparabolic effective-mass approximation and a semiclassical ballistic transport model were used. The capacitance model helped interpret the different contributions of the capacitances, which were due to the inversion-... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy