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Circuits, Devices and Systems, IEE Proceedings G

Issue 5 • Date Oct 1993

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Displaying Results 1 - 10 of 10
  • Efficient computational procedure for the design of FIR digital filters using WLS technique

    Publication Year: 1993 , Page(s): 355 - 359
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The design of an FIR filter using the weighted least-squares (WLS) technique involves solving a Toeplitz matrix problem. However, if the requirement that the impulse response of the filter must be exactly symmetrical is imposed, the matrix becomes non-Toeplitz. The authors point out that it is Toeplitz-plus-Hankel, and present a method with complexity O(N2) for solving the WLS problem. As exact symmetry is imposed on the impulse response, the number of variables to be solved is reduced by about a factor of two. This results in smaller matrices and, as a consequence, the new method uses less computer time per iteration than the Toeplitz case View full abstract»

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  • Electronically tunable filtering networks: theory, analysis and simulation

    Publication Year: 1993 , Page(s): 367 - 372
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A parallel four-port tunable conductance-susceptance network model is proposed for use in tunable filtering networks, with emphasis on its modelling, sensitivity minimising and computer simulation. In contrast with the design of tunable transfer functions in the complex domain, we synthesise a four-port linear and controllable conductance network in the real domain, which is easier to implement with CMOS transconductance elements. The basic building blocks and general forms of the conductance matrix and structure for biquad filtering networks (BFN) are given. The redefined port parameters, equivalent port short-circuit resistance, equivalent port open-circuit resistance and equivalent transfer coefficients are given and used for the analysis of network sensitivity. Theoretical analysis and preliminary simulation results show that the minimum sensitivity condition can be obtained for BFN when the two time constants at two energy-storage ports are equal. It also shows that the ω and Q parameters in biquad filtering networks and the weights in some neural networks are tunable by changing the gate signals, and the input impedance of the network is very large as there is no backward-feed connection to input port. Because the construction is based on CMOS elements, the realisation can be readily integrated. This method can also be used to design a tunable-weight network in some neural networks, since a transconductance element can be easily used as a weight between any two neurons View full abstract»

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  • Graphical block-diagram based programming environment for a DSP silicon compiler

    Publication Year: 1993 , Page(s): 313 - 318
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    The paper presents a graphical block-diagram based programming tool, which is a new software development system for digital signal processing (DSP). This system provides a block-diagram editor; therefore, the DSP system can be easily built by connecting functional blocks as described in the signal-flow graph. A block library is set up, which includes basic signal processing functions and some frequently used high level signal processing functions like FIR, IIR, FFT, etc. A friendly graphic user interface (GUI) based on the `X-Window' system is developed to support each design step. Users can then improve their design easily according to the GUI's response. To guarantee the correctness of the circuits designed, the debugging and verifying capabilities are embedded in our system. The full system is combined with a structural silicon compiler, which we developed previously. Several designs will be illustrated as examples. It has been shown that this tool will be suitable for DSP system design by using a silicon compiler View full abstract»

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  • Insensitive voltage-mode and current-mode filters from commercially available transimpedance opamps

    Publication Year: 1993 , Page(s): 319 - 321
    Cited by:  Papers (16)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    New voltage-mode and current-mode filters implemented from a single commercially available transimpedance operational amplifier are described. The circuits, which exhibit simultaneously two transfer functions (bandpass and lowpass/highpass), are insensitive to active and passive component variations. The author also demonstrates that transimpedance amplifiers including a compensation pin are much more versatile than other topologies. Experimental results obtained using the AD844 from Analog Devices, which confirm the theoretical analysis, are given and discussed View full abstract»

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  • Probability, graphs and electrical networks

    Publication Year: 1993 , Page(s): 347 - 354
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    Explicit forms are presented for the probability that a random tree in a graph G contains any logically expressed set of edges, given that it contains any other logically expressed set of edges. Edge sets may be included or excluded, and may appear in a logical union or intersection. This probability is expressed in terms of various readily calculated or measured resistance values in a resistive electrical network based on G. Explicit expressions are presented for obtaining by inspection the resistance of the above type in a class of structures of considerable application, including, for example, the n-cube used in large-scale computational assemblies View full abstract»

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  • Power digital to analogue conversion using pulse width modulation and digital signal processing

    Publication Year: 1993 , Page(s): 329 - 338
    Cited by:  Papers (4)  |  Patents (6)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    The combination of digital pulse width modulation and oversampled noise shaping is proposed for high quality digital to analogue conversion. High resolution, linearity and efficiency are achieved by converting directly to analogue audio, using class D amplification. Digital signal processing is used to reduce quantisation noise and harmonic distortion at signal frequencies up to 20 kHz. High efficiency is achieved by using MOSFET power switching devices and a pulse repetition rate of 352.8 kHz View full abstract»

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  • Effect of irradiation and annealing conditions on power transistor performance

    Publication Year: 1993 , Page(s): 373 - 376
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    It is shown that to simultaneously achieve requirements of dynamic (storage time) and static (on-resistance, peak drain current) power transistor characteristics, an irradiation/anneal processing cycle may be used. This includes annealing at a temperature range limited by the thermal stabilities of the A-centres and divacancies (i.e. 300-380°C). The irradiation flux by high energy electrons is chosen to accumulate the preassigned concentration of A-centres in the epilayer where transistors have been formed. This condition drives the choice towards high flux irradiation (fluxes above 1016cm-2 ) for SIT power transistors. In addition, the irradiation/annealing process imposes constraints on impurity concentrations in the heavily doped drain (or collector) region and in the epilayer. The shallow donor impurity concentration must greatly exceed the oxygen concentration in the heavily doped region and the oxygen concentration must greatly exceed the carbon concentration in the epilayer View full abstract»

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  • Algorithms for operation scheduling in VLSI circuit design

    Publication Year: 1993 , Page(s): 339 - 346
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    The problem of automatically obtaining the layout of a circuit starting with a purely behavioural specification has been receiving growing attention during the last few years. Several reasons explain this interest, but the main one is the great amount of computing power that can now be integrated in a single device. Modern microelectronic technology allows the realisation in a small area of a great number of functions, enabling the production of very large circuits, whose design cannot be managed properly by traditional tools. So the requirement for new CAD tools, able to assist the designer in the definition of the circuit and to perform complex optimisation tasks is becoming-more and more urgent. While the problems involved in layout definition, floor-planning and channel routing are well known and are solved in several commercially available tools, the automatic design of a VLSI architecture is a much newer matter. In the paper a new algorithm solving one of the main subproblems of the high level synthesis, the operation scheduling, is presented. It is based on a general and flexible probabilistic model, able to manage a wide set of different constraints and optimisation aspects. It is proved, using the main benchmarks available in the literature, that the algorithm gives results comparable with or better than, the best ones published, showing a low time complexity View full abstract»

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  • Improved parallel realisation of IIR adaptive filters

    Publication Year: 1993 , Page(s): 322 - 328
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    A frequency-domain adaptive-filter realisation which uses a parallel arrangement of real second-order IIR sections and preprocessing based on a real orthogonal transform is examined. Experimental results and simulations show that the proposed scheme leads to increased convergence rates and lower computational complexity. The paper also deals with an efficient technique for optimising the convergence factor for the Gauss-Newton algorithms. Some experimental results obtained show that this technique leads to a further increase in the rate of convergence, to improved robustness of the adaptation algorithm, and to reduced mean-square error View full abstract»

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  • Efficient output phase assignment algorithm for PLAs

    Publication Year: 1993 , Page(s): 360 - 366
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    To implement a multiple output function, one has the option to realise each output with either true logic or complementary logic following with an inverter. This paper, proposes an efficient algorithm to solve this output phase assignment problem for PLA implementation. Instead of using the double-phase cover minimisation approach, a property-checking procedure is used to estimate the cost of assignments. With the estimated costs, an assignment with minimum cost is chosen. The experimental results show that the proposed algorithm can obtain excellent assignment compared with other approaches View full abstract»

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