# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 16 of 16

Publication Year: 2012, Page(s): C1
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2012, Page(s): C2
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• ### A 16-$Omega$ Audio Amplifier With 93.8-mW Peak Load Power and 1.43-mW Quiescent Power Consumption

Publication Year: 2012, Page(s):133 - 137
Cited by:  Papers (11)
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A low-distortion three-stage class-AB audio amplifier is designed to drive a 16-Ω headphone speaker load. High power efficiency is achieved using fully differential internal stages with local common-mode feedback and replica biasing of the output stage. The threshold voltage of nMOS transistors was made comparable to that of pMOS transistors by negatively biasing the p-substrate in order to... View full abstract»

• ### A 10-b 100-kS/s 1-mW General-Purpose ADC for Cellular Telephones

Publication Year: 2012, Page(s):138 - 142
Cited by:  Papers (6)
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An on-demand general-purpose analog-to-digital converter (GPADC), which achieves a 10-b accuracy of up to 100-kS/s request rate, is presented. The GPADC can process single-ended signals with selectable input ranges up to the battery voltage. The range selection accuracy is 1 LSB. The DAC architecture presents the benefits of a differential approach while sampling single-ended input signals. Built-... View full abstract»

• ### A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector

Publication Year: 2012, Page(s):143 - 147
Cited by:  Papers (9)  |  Patents (1)
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A new type of sampling error corrector for a time- to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least signif... View full abstract»

• ### An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits

Publication Year: 2012, Page(s):148 - 152
Cited by:  Papers (8)
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An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13 % in the frequency range of 178 kHz ~ 11.3 MHz. The measured peak-to-peak data and clock j... View full abstract»

• ### Design and Stability Analysis of a Low-Voltage Subharmonic Cascode FET Mixer

Publication Year: 2012, Page(s):153 - 157
Cited by:  Papers (2)
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A novel biasing scheme to realize a low-voltage subharmonic cascode FET mixer is presented. The proposed biasing requires a low supply voltage and effectively facilitates the generation of the second harmonic of the local oscillator (LO) signal for subharmonic mixing. Hence, the proposed subharmonic mixer (SHM) exhibits competitive performance at a lower supply voltage compared with conventional S... View full abstract»

• ### An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Publication Year: 2012, Page(s):158 - 162
Cited by:  Papers (29)
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A high-speed and reduced-area 2-D discrete wavelet transform (2-D DWT) architecture is proposed. Previous DWT architectures are mostly based on the modified lifting scheme or the flipping structure. In order to achieve a critical path with only one multiplier, at least four pipelining stages are required for one lifting step, or a large temporal buffer is needed. In this brief, modifications are m... View full abstract»

• ### Efficient Reencoder Architectures for Algebraic Soft-Decision Reed–Solomon Decoding

Publication Year: 2012, Page(s):163 - 167
Cited by:  Papers (3)
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Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. To reduce the complexity of ASD decoders, reencoding and coordinate transformation need to be applied, which require a reencoder and an erasure decoder. In the reencoded and transformed ASD decoders, these two blocks take a significant part of the overall decoder area a... View full abstract»

• ### Analytical Delay Model Considering Variability Effects in Subthreshold Domain

Publication Year: 2012, Page(s):168 - 172
Cited by:  Papers (14)
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The demand of ultralow-power circuits has significantly increased in the last few years. Owing to its great potential in energy savings, the use of supply voltage near or below the transistors' threshold voltages has gained particular attention. Designing these kinds of circuits is still a challenge, particularly when latest advanced process technologies are employed. This brief proposes novel ana... View full abstract»

• ### Low-Voltage CMOS Differential Logic Style With Supply Voltage Approaching Device Threshold

Publication Year: 2012, Page(s):173 - 177
Cited by:  Papers (3)  |  Patents (1)
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This brief describes a novel low-voltage CMOS differential logic operating with supply voltage approaching the MOS threshold voltage. The proposed logic style improves switching speed by boosting the gate-source voltage of transistors along timing-critical signal paths. The logic style also minimizes area overhead by allowing a single boosting circuit to be shared by complementary outputs. Test se... View full abstract»

• ### New Design of 2 $times$ VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

Publication Year: 2012, Page(s):178 - 182
Cited by:  Papers (9)
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A new 2 VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection ... View full abstract»

• ### A New State-Regularized QRRLS Algorithm With a Variable Forgetting Factor

Publication Year: 2012, Page(s):183 - 187
Cited by:  Papers (10)
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This brief proposes a new state-regularized (SR) and QR-decomposition-based (QRD) recursive least squares (RLS) adaptive filtering algorithm with a variable forgetting factor (VFF). It employs the estimated coefficients as prior information to minimize the exponentially weighted observation error, which leads to reduced variance over a conventional RLS algorithm and reduced bias over an L2 View full abstract»

• ### Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer

Publication Year: 2012, Page(s):188 - 192
Cited by:  Papers (1)
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In an analog discrete-time circular buffer forward equalizer (FE), finite bandwidth in the sample-and-hold (S/H) circuit can introduce significant intersymbol interference (ISI) that degrades the FE performance. This brief investigates the effect of the finite S/H bandwidth and presents two methods to equalize the ISI introduced by the finite S/H bandwidth. The first method uses a decision-feedbac... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2012, Page(s): C3
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2012, Page(s): C4
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## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org