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Power Electronics, IET

Issue 3 • Date March 2012

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Displaying Results 1 - 12 of 12
  • Application of Wavelet transform in denoising synchronising signal in line synchronised power electronics converters

    Page(s): 281 - 292
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1570 KB)  

    Line synchronised phase-controlled thyristor power converters produce notches in synchronising signals at the instant of turning on thyristors. These synchronising signals are derived from three-phase supply to generate gate pulses for a converter. The presence of notches leads to malfunctioning of the connected power converters whose operations decisively rely on the proper zero-crossing information of the synchronising signal. Denoising these notches is difficult because of the non-stationary pattern of the synchronising signal. The small drift of supply frequency is the main cause for this non-stationary pattern. A filtering technique based on wavelet transform (WT) is proposed in this work. The application of filtering banks using multi-resolution analysis (MRA) of discrete wavelet transform (DWT) with `Daubechies1` as mother wavelet is found effective in denoising synchronising signals from such noises. The simulation study and the experimental results are presented to justify the proposed filter structure. View full abstract»

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  • Comparison of insulated gate bipolar transistor models for FPGA-based real-timesimulation of electric drives and application guideline

    Page(s): 293 - 303
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    In this study, a comparison of various insulated gate bipolar transistor (IGBT) models for field-programmable gate array (FPGA)-based real-time simulation of power electronic devices is presented. System-level behavioural models include ideal, switching function and averaged models, and the detailed device-level model includes both linear behavioural and non-linear look-up table-based models of IGBT. A three-level 12-pulse voltage source converter system driving a squirrel-cage induction motor has been chosen as the test case system. The entire system including the controller and pulse width modulation (PWM) is implemented on a single FPGA using very high-speed description language in real-time at a fixed time-step of 12.5 ns. The Altera Startix III FPGA is the device used for real-time simulation. Results obtained through all five models are compared and as expected, it has been found that the behaviour-mode simulation is fast but comes with a sacrifice of accuracy and details. A guideline is provided for the users with suggestions, so that the right kind of model can be selected for a particular study. View full abstract»

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  • Low-frequency dynamic modelling and control of matrix converter for power system applications

    Page(s): 304 - 314
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1318 KB)  

    High-power density of a matrix converter (MC) necessarily introduces tight dynamic input-output coupling, which complicates controller design for high bandwidth applications. Strong contemporary interest in MC-based solutions for synchronous, power system applications demands high dynamic performance out of the MC, operated as a closed-loop system. The requisite system models reported either treat the MC - with its input and output filters - as a -black-box- characterised by a set of eigenvalues, derived from linearised analysis around an equilibrium point. Alternatively, large-signal system analysis was reported for a feed-forward control approach with prescription of a throughput power boundary for stable operation. This study provides a designer-s insight into MC modelling, based on linearised analysis, clearly establishing the influence of individual physical sub-systems on the overall dynamic performance. Onset of a cluster of right-half zeros, decided solely by the input filter, power factor, source voltage and power throughput, is shown to be the only factor threatening closed-loop stability. Subsequently, a controller with output feedback is designed to ensure stable operation well beyond the throughput power limit prescribed earlier. Comprehensive simulation and experimental results are provided to validate the analytical model and controller design. View full abstract»

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  • On-line fault detection of aluminium electrolytic capacitors, in step-down DC-DC converters, using input current and output voltage ripple

    Page(s): 315 - 322
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (541 KB)  

    The aim of this study is to present a simple on-line fault detection technique that is able to prevent structural failures in aluminium electrolytic capacitors used in the output filter of step-down DC-DC converters. The aluminium electrolytic capacitors equivalent circuit consists of an ideal resistance in series with an ideal capacitor and an ideal inductor. The first two elements change with frequency, temperature and aging. Most manufacturers define the end of life limit of these capacitors when their internal resistance (equivalent series resistance (ESR)) doubles or their capacitance (C) reduces by 20%, when compared with the initial values. The proposed on-line fault detection technique is able to estimate the capacitor ESR value during converter operation. For that purpose, a simple relationship between the input current and the output voltage ripple is used. The measurement system is composed of a digital oscilloscope that is connected to a microcomputer with %Matlab% software. Several simulation and experimental results are presented to validate the proposed fault detection technique. View full abstract»

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  • Weight factor selection for model-based predictive control of a four-level flying-capacitor inverter

    Page(s): 323 - 333
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1050 KB)  

    Flying-capacitor (FC) converters need, besides an output current control, a control of the FC voltages to be able to produce appropriate output voltage levels. The output currents and capacitor voltages can be actively controlled by model-based predictive control (MBPC). This MBPC has several control parameters such as weight factors in the cost function. The selection of these weight factors and other control parameters of MBPC is not trivial and needs an objective criterion. A method using mean square error (MSE) values of the controlled variables is proposed. The feasibility of the MBPC and the MSE analysis method for multilevel inverters is demonstrated by experiments. The good correspondence between simulations and experiments clearly shows that the results from a design analysis of MBPC in simulation is applicable on the practical setup. Two models in the prediction step of the MBPC are discussed in this study: using a simplified model, where the star-point voltage is neglected, and using an unsimplified model. The simplification, although reducing the computational requirements, results in suboptimal control quality and more importantly a less robust control. The experiments validate the conclusion that using the unsimplified model extends the range of good weight factors and improves the control quality of the current and capacitor voltages. View full abstract»

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  • Soft switching bridgeless power factor correction with reduced conduction losses and no stresses

    Page(s): 334 - 340
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    In this study, a new soft switching high power factor (PF) bridgeless rectifier with PWM control is introduced. The converter employs an auxiliary circuit providing soft switching for all semiconductor devices without any extra current and voltage stress on the switches. Also, in all operation modes, the power path is provided by maximum two semiconductor elements. Thus, the switching and conduction losses are reduced and maximum efficiency is achieved. The converter is designed, simulated and a 500 W prototype is implemented to verify the system performance. The experimental results exhibit high PF and efficiency of the proposed converter. View full abstract»

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  • Adaptive digital proportional-integral-derivative controller for power converters

    Page(s): 341 - 348
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (738 KB)  

    An adaptive digital proportional-integral-derivative (AD-PID) controller scheme is presented in this study to improve the dynamic performance of power converters. The controller adaptively adjusts the integral constant (Ki) and the proportional constant (Kp) following a new control law. The control law is a function of the magnitude change in the error signal and its peak value during dynamic transients. The proposed AD-PID controller adaptively detects the peak value of the error signal, which is a function of the transient nature and magnitude and utilises it in the control law such that no oscillations are generated as a result of the adaptive operation. As a result, the dynamic output voltage deviation and the settling time of the output voltage are reduced. The concept and architecture of the proposed AD-PID are presented and its proposed control law is discussed and verified by experimental results obtained from a single-phase DC-DC buck converter with input voltage range of 8-10-V, nominal output voltage of 1.5-V and a maximum load current of 7-A. View full abstract»

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  • Flyback-based high step-up converter with reduced power processing stages

    Page(s): 349 - 357
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (813 KB)  

    This study proposes a non-isolated converter derived from the conventional flyback topology based on the concept of reduced power processing. The proposed converter has higher-voltage gain, improved efficiency and reduced component stresses owing to recycling of leakage energy and clamped power switch voltage when compared with the conventional flyback converter, and yet retains the advantages of circuit simplicity and low cost. A complete analysis including converter operation and its dc and ac characterisations are presented in the paper. Using a 60 W laboratory prototype operating at 100 kHz with 24 V input voltage and 200 V regulated output voltage, experimental evaluation of the efficiency improvement, steady-state and transient-response performance are presented to verify the effectiveness of the proposed converter. View full abstract»

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  • Single inductor three-level bridgeless boost power factor correction rectifier with nature voltage clamp

    Page(s): 358 - 365
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    This study proposes a single-phase bridgeless three-level boost power factor correction (PFC) converter with nature voltage clamp. The proposed converter can be treated as two boost converters in series, and the charging and the discharging of the inductor are performed in different boost sub-circuits. Two slow diodes are used as rectifier diodes and voltage clamping diodes at the same time. As a result, nature voltage clamp is achieved. Furthermore, the proposed converter has high device utilisation factor and requires only one inductor, which simplifies the whole circuit. The detailed operational principle and design consideration are discussed. A 1 kW experimental prototype with universal input is built to verify the theoretical analysis. The result shows that the efficiency is above 94 at full load under 90 V line input and the maximum efficiency is 98.4 . View full abstract»

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  • Common-mode voltage reduction in a motor drive system with a power factor correction

    Page(s): 366 - 375
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1447 KB)  

    Common-mode voltage generated by a power converter in combination with parasitic capacitive couplings is a potential source of shaft voltage in an AC motor drive system. In this study, a three-phase motor drive system supplied with a single-phase AC-DC diode rectifier is investigated in order to reduce shaft voltage in a three-phase AC motor drive system. In this topology, the AC-DC diode rectifier influences the common-mode voltage generated by the inverter because the placement of the neutral point is changing in different rectifier circuit states. A pulse width modulation technique is presented by a proper placement of the zero vectors to reduce the common-mode voltage level, which leads to a cost-effective shaft voltage reduction technique without load current distortion, while keeping the switching frequency constant. Analysis, simulations and experimental implementation have been presented to investigate the proposed method. View full abstract»

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  • Current sharing in multiphase zero-voltage transition boost converter

    Page(s): 376 - 384
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    The zero-voltage transition (ZVT) boost converter has been analysed and a complete model has been obtained. It has been checked it behaves as a voltage source with high impedance and, because of this property, it is a valid topology for multiphase design, where different stages will share load in a passive way, without any extra mechanism or components to achieve load sharing. The design of multiphase converters is simplified, especially for a big number of phases, as no extra information must be processed. Steady-state current sharing has been studied and how components tolerances will affect to current distribution. A simple design guide to select different components has been detailed. To test passive current sharing a two-phase 600 W prototype has been built and it has been tested in open loop. This has been done to prove that without control loop or extra components there is load sharing when ZVT converters are connected in parallel. View full abstract»

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  • Z-source-based multilevel inverter with reduction of switches

    Page(s): 385 - 392
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (946 KB)  

    This study presents a new inverter topology based on mixture of cascaded basic units and one H-bridge unit. The basic unit includes one Z source, one DC voltage source and two switches generating two voltage levels. The cascaded basic units produce positive and zero-voltage levels and in the same time suggested inverter obtains positive, zero- and negative voltage levels, as a result the number of power semiconductor switches is reduced with respect to traditional multilevel inverters. In this topology, output voltage amplitude is not limited to DC sources voltage summation similar to traditional cascaded multilevel inverters and can be boosted with Z network shoot-through state control; therefore other DC/DC converters are not needed and it is more reliable against short circuit. Besides as compared with traditional Z-source inverter, total harmonic distortion of injected voltage is decreased in the suggested inverter topology. The performance of proposed topology and its controller are validated with simulation results using MATLAB/SIMULINK software and the validity of the proposed multilevel inverter-based Z source is verified by experimental results. View full abstract»

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Aims & Scope

IET Power Electronics brings together five principal power electronics themes including: applications of power semiconductor technology; circuits; devices; techniques; and performance management.

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