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# IEEE Transactions on Device and Materials Reliability

## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2012, Page(s):C1 - C4
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• ### IEEE Transactions on Device and Materials Reliability publication information

Publication Year: 2012, Page(s): C2
| PDF (36 KB)
• ### Changes to the Editorial Board

Publication Year: 2012, Page(s):1 - 3
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• ### Lifetime Estimation for Plastic Optical Fibers in Harsh Acid Environments

Publication Year: 2012, Page(s):4 - 9
Cited by:  Papers (1)
| | PDF (444 KB) | HTML

The work described in this paper explores the suitability of using plastic optical fibers (POFs) as sensors for the development of fast battery chargers. Lead-acid batteries, widely used in the automotive industry, contain an electrolyte formed by a high concentration of sulfuric acid (35% ), an acid environment that can maintain an elevated temperature during the charge and discharge processes. T... View full abstract»

• ### Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection

Publication Year: 2012, Page(s):10 - 14
Cited by:  Papers (11)  |  Patents (2)
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Diode-triggered silicon-controlled rectifiers (DTSCRs) are used for on-chip electrostatic discharge protection. The role of the trigger diode string in determining the transient voltage overshoot is investigated using a very fast transmission line pulse. A DTSCR containing only poly-bound trigger diodes has a voltage overshoot of just 1.5 V at 7 A, which is significantly less than what is found wi... View full abstract»

• ### Domed and Released Thin-Film Construct—An Approach for Material Characterization and Compliant Interconnects

Publication Year: 2012, Page(s):15 - 23
Cited by:  Papers (5)
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An approach for microfabricating precisely defined spherical 3-D domes through a simple low-temperature polymer reflow process was developed. Release of a thin metal film patterned over the domed structure was accomplished by the removal of the underlying polymer using two different methods: dry thermal decomposition and wet supercritical release. The domed shape impacted the effect of stiction du... View full abstract»

• ### Read Performance Reliability in TMR Head

Publication Year: 2012, Page(s):24 - 30
Cited by:  Papers (1)
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Causes of head instability and design improvements in tunneling magnetoresistive heads are discussed. Head instability results in output signal amplitude changes and/or signal distortion due to the output noise. Under accelerated environmental conditions, a test using an original "V-H tester” was done to study and analyze the conditions of which instability occurs. From the result of the te... View full abstract»

• ### Study of RF Reliability of GaN HEMTs Using Low-Frequency Noise Spectroscopy

Publication Year: 2012, Page(s):31 - 36
Cited by:  Papers (7)
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The results of continuous wave short-term RF stress applied at 3 GHz on GaN high electron mobility transistors on silicon substrate are presented. The degradation of the device characteristics for RF overdrive conditions from 3-dB to 8-dB gain saturation is discussed. Output RF power degrades significantly in a short period of time. Both transient and permanent degradation of electronic properties... View full abstract»

• ### Analysis of Main Degradation in Lasers With p-/n-Type InP Buried Layers Using OBIC Technique

Publication Year: 2012, Page(s):37 - 43
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The main degradation of the t0.5 deterioration property (second-stage degradation) in lasers during constant-power aging is investigated by using the optical beam-induced current technique. We clarify that defects that cause this second-stage degradation diffuse mainly from around the regrown interface of the p-type InP cladding layer above the active layer to the active layer via the s... View full abstract»

• ### Rapid Light Output Degradation of GaN-Based Packaged LED in the Early Stage of Humidity Test

Publication Year: 2012, Page(s):44 - 48
Cited by:  Papers (9)
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An initial sharp decrease in the light output of a high-power light-emitting diode is observed when it is exposed to humid condition. TGA and energy-dispersive system analyses confirm the possibility of moisture entrapment in the silicone encapsulation; moreover, the light scattering model verifies qualitatively the scattering of the light due to the entrapped moisture, and it is this scattering t... View full abstract»

• ### Prognostics of Multilayer Ceramic Capacitors Via the Parameter Residuals

Publication Year: 2012, Page(s):49 - 57
Cited by:  Papers (4)
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This paper presents a parameter residual-based method for predicting the remaining useful life (RUL) of multilayer ceramic capacitors (MLCCs) under temperature-humidity-bias conditions. Three performance parameters in each MLCC were monitored: capacitance, dissipation factor, and insulation resistance. A kernel regression method was used to estimate the parameters' values of interest. The residual... View full abstract»

• ### Bias-Stress-Induced Instability of Polymer Thin-Film Transistor Based on Poly(3-Hexylthiophene)

Publication Year: 2012, Page(s):58 - 62
Cited by:  Papers (11)
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A polymer thin-film transistor (PTFT) based on poly(3-hexylthiophene) (P3HT) is fabricated by a spin-coating process and characterized. Its bias-stress-induced instability during operation is investigated as a function of time and temperature. For negative gate-bias stress, the carrier mobility remains unchanged, the off-state current decreases, and the threshold voltage shifts toward the negative... View full abstract»

• ### Temperature Dependence of Hysteresis Effect in Partially Depleted Silicon-on-Insulator MOSFETs

Publication Year: 2012, Page(s):63 - 67
Cited by:  Papers (7)
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The hysteresis effect on the output characteristics, which originates from the floating-body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, at different temperatures between 25 °C and 125 °C. For a better understanding of the hysteresis characteristics, the authors developed ID hysteresis which is defined as the difference between ... View full abstract»

• ### Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Publication Year: 2012, Page(s):68 - 77
Cited by:  Papers (19)
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The occurrence of a single event with a multiple-node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis, and design) for hardening storage elements (memories and latches) against a soft error resulting in a multiple-node upset at 32-nm feature size in CMOS. A novel ... View full abstract»

• ### Circuit Design-Oriented Stochastic Piecewise Modeling of the Postbreakdown Gate Current in MOSFETs: Application to Ring Oscillators

Publication Year: 2012, Page(s):78 - 85
Cited by:  Papers (7)
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A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemente... View full abstract»

• ### Reliability of Embedded Planar Capacitors With Epoxy– $hbox{BaTiO}_{3}$ Composite Dielectric During Temperature–Humidity–Bias Tests

Publication Year: 2012, Page(s):86 - 93
Cited by:  Papers (5)
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In this work, the reliability of an embedded planar capacitor with epoxy-BaTiO3 composite dielectric was investigated under temperature-humidity-bias (THB) conditions. The temperature and humidity conditions were selected as 85°C and 85% RH, respectively. In order to investigate the effect of an applied bias, one set of capacitors was kept unbiased, and the other set of capacitor... View full abstract»

• ### Defect Behaviors During High Electric Field Stress of p-Channel Power MOSFETs

Publication Year: 2012, Page(s):94 - 100
Cited by:  Papers (2)
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The behaviors of the defects in the oxide, near and at the interface during various electric field stress experiments of commercial p-channel power VDMOSFETs, have been investigated. High electric field stress (HEFS), switching HEFS, and switching electric field annealing have been performed. The results have shown that the creations of both the positively charged fixed traps (FTs) (PCFTs) and neg... View full abstract»

• ### A (64,45) Triple Error Correction Code for Memory Applications

Publication Year: 2012, Page(s):101 - 106
Cited by:  Papers (11)
| | PDF (146 KB) | HTML

Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-s... View full abstract»

• ### Effects of Annealing Temperature and Gas on Pentacene OTFTs With HfLaO as Gate Dielectric

Publication Year: 2012, Page(s):107 - 112
Cited by:  Papers (2)
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Pentacene organic thin-film transistors (OTFTs) with high-κ HfLaO as gate insulator were fabricated. HfLaO film was prepared by sputtering method. To improve the film quality, the dielectric was annealed in N2, NH3, or O2 at two temperatures, i.e., 200°C and 400°C, respectively. The I-V characteristics of the OTFTs and C-V characteristics of co... View full abstract»

• ### An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

Publication Year: 2012, Page(s):113 - 123
Cited by:  Papers (13)
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A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 μm high-voltage 10 V process. This device consists simply of a floating P+ diffusion incorporated in a parasitic NPN BJT. A robust 6-7 kV ESD threshold and high-latchup-immune holding voltage of 15-18 V can be achieved by layout optimi... View full abstract»

• ### Transient Thermal Performance of IGBT Power Modules Attached by Low-Temperature Sintered Nanosilver

Publication Year: 2012, Page(s):124 - 132
Cited by:  Papers (29)
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Recently, to accurately study the transient thermal behavior of power modules, a transient thermal measurement system was developed to investigate the transient thermal behavior of insulated-gate bipolar transistor (IGBT) modules attached by nanosilver paste and two kinds of lead-free solders. We found that the transient thermal impedance of IGBT modules attached by nanosilver paste was 9% lower t... View full abstract»

• ### Degradation Processes in Surface Layers of Indium Oxide

Publication Year: 2012, Page(s):133 - 138
Cited by:  Papers (1)
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The degradation of In2O3 (110) surface as a working surface in the In2O3-based sensor is studied. Theoretical and experimental investigations of electronic and atomic processes on this surface caused by the adsorption H2 of molecules are performed. In the framework of the density functional theory, we determined the energetically preferable po... View full abstract»

• ### Gate-Geometric Recessed Nanoscale $hbox{In}_{0.52} hbox{Al}_{0.48}hbox{As}$–$hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ Double-Gate HEMT for High Breakdown

Publication Year: 2012, Page(s):139 - 145
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In this paper, a generalized analysis of recessed double-gate high-electron-mobility transistor for different gate geometries (T-gate, IL-gate, Γ-gate, etc.) to realize higher breakdown is carried out. The effect of gate geometries on breakdown voltage is studied through potential and electric field profile. The drain current, transconductance, intrinsic gain, capacitances, and RF performan... View full abstract»

• ### The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

Publication Year: 2012, Page(s):146 - 151
Cited by:  Papers (7)
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In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimenta... View full abstract»

• ### Modeling of Charge-Trapping/Detrapping-Induced Voltage Instability in High- $k$ Gate Dielectrics

Publication Year: 2012, Page(s):152 - 157
Cited by:  Papers (2)
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Investigation of trapping-/detrapping-induced volt- age instabilities does demand not only accurate measurements but also a precise methodology for extracting the exact magnitude of the voltage shifts in the hysteresis curves which is indispensable. Particularly, in dc measurements where the induced voltage shifts are small, an excellent accuracy of the analysis method is required. Therefore, in t... View full abstract»

## Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.