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Device and Materials Reliability, IEEE Transactions on

Issue 1 • Date March 2012

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  • Table of contents

    Publication Year: 2012 , Page(s): C1 - C4
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  • IEEE Transactions on Device and Materials Reliability publication information

    Publication Year: 2012 , Page(s): C2
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  • Changes to the Editorial Board

    Publication Year: 2012 , Page(s): 1 - 3
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  • Lifetime Estimation for Plastic Optical Fibers in Harsh Acid Environments

    Publication Year: 2012 , Page(s): 4 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    The work described in this paper explores the suitability of using plastic optical fibers (POFs) as sensors for the development of fast battery chargers. Lead-acid batteries, widely used in the automotive industry, contain an electrolyte formed by a high concentration of sulfuric acid (35% ), an acid environment that can maintain an elevated temperature during the charge and discharge processes. This presents a challenge for the selection of sensors that can withstand such harsh conditions over extended periods of time, in order to monitor the charge cycle and state of health of the battery. POFs can be used as density sensors immersed in the electrolyte at different places within the battery-density varies with location. The accuracy of the density readout must be maintained throughout the useful life of the battery, up to 15 years. In this paper, we present results of over 9000 h of lifetime tests of POFs used as sensing elements for electrolyte density, as well as a procedure to estimate their lifetime for the target application. View full abstract»

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  • Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection

    Publication Year: 2012 , Page(s): 10 - 14
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB) |  | HTML iconHTML  

    Diode-triggered silicon-controlled rectifiers (DTSCRs) are used for on-chip electrostatic discharge protection. The role of the trigger diode string in determining the transient voltage overshoot is investigated using a very fast transmission line pulse. A DTSCR containing only poly-bound trigger diodes has a voltage overshoot of just 1.5 V at 7 A, which is significantly less than what is found with STI-bound diodes. A DTSCR with only STI-bound trigger diodes has a lower leakage current. Therefore, DTSCRs with different trigger diode configurations may be suitable for different applications, e.g., high speed or low power. View full abstract»

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  • Domed and Released Thin-Film Construct—An Approach for Material Characterization and Compliant Interconnects

    Publication Year: 2012 , Page(s): 15 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (723 KB) |  | HTML iconHTML  

    An approach for microfabricating precisely defined spherical 3-D domes through a simple low-temperature polymer reflow process was developed. Release of a thin metal film patterned over the domed structure was accomplished by the removal of the underlying polymer using two different methods: dry thermal decomposition and wet supercritical release. The domed shape impacted the effect of stiction during the release step and assisted in the release of large millimeter-size film geometries. The dome and release procedures were used to fabricate an experimental test specimen that functions as either a tensile or interfacial fracture test for thin films on rigid substrates. Other potential applications of the domed metal structures such as compliant electrical interconnects are discussed. View full abstract»

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  • Read Performance Reliability in TMR Head

    Publication Year: 2012 , Page(s): 24 - 30
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1232 KB) |  | HTML iconHTML  

    Causes of head instability and design improvements in tunneling magnetoresistive heads are discussed. Head instability results in output signal amplitude changes and/or signal distortion due to the output noise. Under accelerated environmental conditions, a test using an original "V-H tester” was done to study and analyze the conditions of which instability occurs. From the result of the test, instability was classified into four categories. The improved sample heads were prepared, and the effectiveness was proved. View full abstract»

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  • Study of RF Reliability of GaN HEMTs Using Low-Frequency Noise Spectroscopy

    Publication Year: 2012 , Page(s): 31 - 36
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1157 KB) |  | HTML iconHTML  

    The results of continuous wave short-term RF stress applied at 3 GHz on GaN high electron mobility transistors on silicon substrate are presented. The degradation of the device characteristics for RF overdrive conditions from 3-dB to 8-dB gain saturation is discussed. Output RF power degrades significantly in a short period of time. Both transient and permanent degradation of electronic properties of the device are identified. After high RF gain compression levels, DC characteristics like the threshold voltage and gate leakage current change permanently. Detailed microscopic changes in the electronic structure of the device were studied by performing simultaneous low-frequency noise measurements of gate and drain currents before and after stress. The channel was found to be immune to the whole stress regime with no increase of the Hooge parameter. On the other hand, activation of unstable defects and then an increase of the defect density near the gate metal semiconductor interface were observed from gate noise measurements. A point defect located at around 4.5 nm from the gate metal semiconductor interface with activation energy of 0.9 eV below the AlGaN conduction band edge was determined from random telegraph noise measurements. The role of forward gate biasing as a failure mechanism is also discussed. View full abstract»

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  • Analysis of Main Degradation in Lasers With p-/n-Type InP Buried Layers Using OBIC Technique

    Publication Year: 2012 , Page(s): 37 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (673 KB) |  | HTML iconHTML  

    The main degradation of the t0.5 deterioration property (second-stage degradation) in lasers during constant-power aging is investigated by using the optical beam-induced current technique. We clarify that defects that cause this second-stage degradation diffuse mainly from around the regrown interface of the p-type InP cladding layer above the active layer to the active layer via the separate confinement heterostructure layer. View full abstract»

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  • Rapid Light Output Degradation of GaN-Based Packaged LED in the Early Stage of Humidity Test

    Publication Year: 2012 , Page(s): 44 - 48
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB) |  | HTML iconHTML  

    An initial sharp decrease in the light output of a high-power light-emitting diode is observed when it is exposed to humid condition. TGA and energy-dispersive system analyses confirm the possibility of moisture entrapment in the silicone encapsulation; moreover, the light scattering model verifies qualitatively the scattering of the light due to the entrapped moisture, and it is this scattering that renders an initial sharp drop in the light output. The finding shows the importance of pore size of the silicone gel in order to prevent such sharp decrease in the light output under a humid environment. View full abstract»

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  • Prognostics of Multilayer Ceramic Capacitors Via the Parameter Residuals

    Publication Year: 2012 , Page(s): 49 - 57
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (956 KB) |  | HTML iconHTML  

    This paper presents a parameter residual-based method for predicting the remaining useful life (RUL) of multilayer ceramic capacitors (MLCCs) under temperature-humidity-bias conditions. Three performance parameters in each MLCC were monitored: capacitance, dissipation factor, and insulation resistance. A kernel regression method was used to estimate the parameters' values of interest. The residuals were generated by the difference between the estimation and the actual monitored value. Based on the features of the residual data, a linear state space model was adopted to describe the dynamics of the residuals. The future evolution of the residuals was predicted with uncertainty bounds in a Bayesian framework. The failure threshold in terms of the parameter residuals was investigated. Then, the RUL of each MLCC with uncertainty bounds was determined. By comparing the predicted results with the experimental results, it was demonstrated that the proposed prognostics approach can provide an estimation of the RUL of MLCCs. View full abstract»

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  • Bias-Stress-Induced Instability of Polymer Thin-Film Transistor Based on Poly(3-Hexylthiophene)

    Publication Year: 2012 , Page(s): 58 - 62
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (567 KB) |  | HTML iconHTML  

    A polymer thin-film transistor (PTFT) based on poly(3-hexylthiophene) (P3HT) is fabricated by a spin-coating process and characterized. Its bias-stress-induced instability during operation is investigated as a function of time and temperature. For negative gate-bias stress, the carrier mobility remains unchanged, the off-state current decreases, and the threshold voltage shifts toward the negative direction. On the other hand, for negative drain-bias stress, the carrier mobility decreases slightly, the off-state current increases, and the threshold voltage shifts toward the positive direction. The threshold shifts under gate- and drain-bias stresses are observed to be logarithmically dependent on time, and the decay rate of the threshold-voltage shift is independent of temperature. The results suggest that the origin of the threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the gate dielectric or at the interface, while time-dependent charge trapping in the deep trap states and creation of defect states in the channel region are responsible for the drain-bias stress effect on the PTFT. View full abstract»

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  • Temperature Dependence of Hysteresis Effect in Partially Depleted Silicon-on-Insulator MOSFETs

    Publication Year: 2012 , Page(s): 63 - 67
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB) |  | HTML iconHTML  

    The hysteresis effect on the output characteristics, which originates from the floating-body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, at different temperatures between 25 °C and 125 °C. For a better understanding of the hysteresis characteristics, the authors developed ID hysteresis which is defined as the difference between ID versus VD forward sweep and reverse sweep. The fabricated devices show positive and negative peaks in Id hysteresis. The experimental results show that ID hysteresis declined as the operating temperature increases. Based on the measurement, we have demonstrated the temperature dependence of hysteresis effect in PD SOI MOSFETs. View full abstract»

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  • Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

    Publication Year: 2012 , Page(s): 68 - 77
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    The occurrence of a single event with a multiple-node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis, and design) for hardening storage elements (memories and latches) against a soft error resulting in a multiple-node upset at 32-nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple-node upset. The proposed hardened memory cell utilizes a Schmitt trigger (ST) design. As evidenced in past technical literature and used in this work, simulation of all node pairs by current sources results in an assessment similar to 3-D device tools; the simulation results show that the proposed 13T improves substantially over DICE in the likely and realistic scenarios of very diffused or limited charge sharing/collection. Moreover, the 13T cell achieves a 33% reduction in write delay and only a 5% (9%) increase in power consumption (layout area) compared to the DICE cell (consisting of 12 transistors). The analysis is also extended to hardened latches; it is shown that the latch with the highest critical charge has also the best tolerance to a multiple-node upset. Among the hardened latches, the ST designs have the best tolerance, and in particular, the transmission gate configuration is shown to be the most effective. Simulation results are provided using the predictive technology file for 32-nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple-node upset tolerance of the proposed hardened storage elements in the presence of process, voltage, and temperature variations in their designs. View full abstract»

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  • Circuit Design-Oriented Stochastic Piecewise Modeling of the Postbreakdown Gate Current in MOSFETs: Application to Ring Oscillators

    Publication Year: 2012 , Page(s): 78 - 85
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB) |  | HTML iconHTML  

    A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example. View full abstract»

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  • Reliability of Embedded Planar Capacitors With Epoxy– \hbox {BaTiO}_{3} Composite Dielectric During Temperature–Humidity–Bias Tests

    Publication Year: 2012 , Page(s): 86 - 93
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (933 KB) |  | HTML iconHTML  

    In this work, the reliability of an embedded planar capacitor with epoxy-BaTiO3 composite dielectric was investigated under temperature-humidity-bias (THB) conditions. The temperature and humidity conditions were selected as 85°C and 85% RH, respectively. In order to investigate the effect of an applied bias, one set of capacitors was kept unbiased, and the other set of capacitors was biased at 5 V. Capacitors of two different sizes were used to investigate the effect of area on reliability under these conditions. Three parameters-capacitance, dissipation factor, and insulation resistance-were monitored in situ every hour during the THB test, which lasted for 2000 h. Data analysis and the physical explanation of change in the electrical parameters under THB conditions are presented in this paper. View full abstract»

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  • Defect Behaviors During High Electric Field Stress of p-Channel Power MOSFETs

    Publication Year: 2012 , Page(s): 94 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB) |  | HTML iconHTML  

    The behaviors of the defects in the oxide, near and at the interface during various electric field stress experiments of commercial p-channel power VDMOSFETs, have been investigated. High electric field stress (HEFS), switching HEFS, and switching electric field annealing have been performed. The results have shown that the creations of both the positively charged fixed traps (FTs) (PCFTs) and negatively charged FTs (NCFTs) are more intensive in the case of positive HEFS than negative HEFS. The intermediate steps with low electric field stress do not significantly influence the defect creations in positive HEFS but do influence those in negative HEFS. The slow switching (border) traps have the same nature as FTs, and the same defect types are responsible for PCFT creation during positive and negative HEFSs. View full abstract»

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  • A (64,45) Triple Error Correction Code for Memory Applications

    Publication Year: 2012 , Page(s): 101 - 106
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (146 KB) |  | HTML iconHTML  

    Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as difference-set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs. View full abstract»

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  • Effects of Annealing Temperature and Gas on Pentacene OTFTs With HfLaO as Gate Dielectric

    Publication Year: 2012 , Page(s): 107 - 112
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB) |  | HTML iconHTML  

    Pentacene organic thin-film transistors (OTFTs) with high-κ HfLaO as gate insulator were fabricated. HfLaO film was prepared by sputtering method. To improve the film quality, the dielectric was annealed in N2, NH3, or O2 at two temperatures, i.e., 200°C and 400°C, respectively. The I-V characteristics of the OTFTs and C-V characteristics of corresponding organic capacitors were measured. The OTFTs could operate at a low operating voltage of below 5 V, and the dielectric constant of the HfLaO film could be above ten. For all the annealing gases, the OTFTs annealed at 400°C achieved higher carrier mobility than their counterparts annealed at 200°C (with the one annealed in NH3 at 400°C showing the highest carrier mobility of 0.45 cm2/V · s), which could be supported by SEM images which indicate that pentacene tended to form larger grains on HfLaO annealed at 400°C than on that annealed at 200°C. The C-V measurement of the organic capacitors indicated that the localized charge density in the organic semiconductor/oxide was lower for the 400°C annealing than for the 200°C annealing. Furthermore, through the characterization of gate current leakage, HfLaO film annealed at 400°C achieved much smaller leakage than that annealed at 200°C. Since the maximum processing temperature of ITO glass substrates is around 400°C, this study shows that 400°C is suitable for the annealing of HfLaO film in high- performance OTFTs on glass substrate. View full abstract»

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  • An SCR-Incorporated BJT Device for Robust ESD Protection With High Latchup Immunity in High-Voltage Technology

    Publication Year: 2012 , Page(s): 113 - 123
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1213 KB) |  | HTML iconHTML  

    A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 μm high-voltage 10 V process. This device consists simply of a floating P+ diffusion incorporated in a parasitic NPN BJT. A robust 6-7 kV ESD threshold and high-latchup-immune holding voltage of 15-18 V can be achieved by layout optimization of the NPN-N+ -collector to floating P+ -diffusion spacing and the floating P+ diffusion width. It can be equivalently regarded as parallel connection of an incorporated PNPN SCR part and an NPN BJT part. The incorporated SCR part is further composed of a parasitic SCR in series with a reverse-biased PN diode formed by the floating P+ region and N-well. The further analysis shows that the floating P+ diffusion is the key part of this SCR-incorporated BJT. The parasitic reverse-biased PN diode sustains most of the high holding voltage. The parasitic NPN BJT plays a major role in ESD current conduction, while the incorporated SCR in series with the reverse-biased PN diode is the secondary conduction path. View full abstract»

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  • Transient Thermal Performance of IGBT Power Modules Attached by Low-Temperature Sintered Nanosilver

    Publication Year: 2012 , Page(s): 124 - 132
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1019 KB) |  | HTML iconHTML  

    Recently, to accurately study the transient thermal behavior of power modules, a transient thermal measurement system was developed to investigate the transient thermal behavior of insulated-gate bipolar transistor (IGBT) modules attached by nanosilver paste and two kinds of lead-free solders. We found that the transient thermal impedance of IGBT modules attached by nanosilver paste was 9% lower than that of the modules using SAC305 and SN100C with 40-ms heating pulse. In addition, finite-element analysis is employed to simulate thermal performance of the IGBT devices. The simulation shows that the transient thermal impedance of IGBT modules attached by nanosilver paste was also lower than that of the modules using lead-free solders. A convenient way was introduced to well predict the transient thermal behavior of IGBT power module. The calculated results agreed well with the measured one. The interface thermal impedance of sintered nanosilver and SNC100C are calculated to be 0.011 ~ 0.031 K/W and 0.022 ~ 0.042 K/W, respectively. View full abstract»

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  • Degradation Processes in Surface Layers of Indium Oxide

    Publication Year: 2012 , Page(s): 133 - 138
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (437 KB) |  | HTML iconHTML  

    The degradation of In2O3 (110) surface as a working surface in the In2O3-based sensor is studied. Theoretical and experimental investigations of electronic and atomic processes on this surface caused by the adsorption H2 of molecules are performed. In the framework of the density functional theory, we determined the energetically preferable position of the adsorbed H2 molecule over In2O3 surface. It was found that the adsorbed H2 molecule is mainly “bonded” with In atom. The redistribution of the electron density around In atom leads to a weakening of chemical bonds in the vicinity of In atom, and this circumstance is a reason of its destabilization. The temperature dependence of the resistance In2O3 of films in a wide interval of temperatures was measured. This dependence is characterized by a specific maximum. The obtained experimental results are interpreted using theoretical results concerning a destabilization of surface In atoms induced by the adsorbed H2 molecules and, on the basis of our recent results in an earlier paper, concerning a high-temperature degradation of the In2O3 (110) surface layers as a working surface in sensor devices. We suggested a two-stage model of the degradation process: In the first stage, the disordering of surface caused by H2-adsorption-stimulated displacement of In atoms leads to the increase of surface resistance, and in the second stage, displaced In atoms form precipitates and this process causes a metallization In2O3 of surface and a decrease of the resistance. View full abstract»

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  • Gate-Geometric Recessed Nanoscale \hbox {In}_{0.52} \hbox {Al}_{0.48}\hbox {As} \hbox {In}_{0.53} \hbox {Ga}_{0.47}\hbox {As} Double-Gate HEMT for High Breakdown

    Publication Year: 2012 , Page(s): 139 - 145
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1001 KB) |  | HTML iconHTML  

    In this paper, a generalized analysis of recessed double-gate high-electron-mobility transistor for different gate geometries (T-gate, IL-gate, Γ-gate, etc.) to realize higher breakdown is carried out. The effect of gate geometries on breakdown voltage is studied through potential and electric field profile. The drain current, transconductance, intrinsic gain, capacitances, and RF performances are also studied. The analysis shows that the incorporation of these geometries not only leads to higher breakdown but also enhances the transcapacitance of the devices, which affect the device RF performance. View full abstract»

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  • The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

    Publication Year: 2012 , Page(s): 146 - 151
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (963 KB) |  | HTML iconHTML  

    In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimental results demonstrate that the LIGBT with runway layout achieves excellent thermal breakdown current of more than 10 A with 250-μm device width. The high ESD performance enables the LIGBT to be used as a promising ESD protection device in the power ICs. View full abstract»

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  • Modeling of Charge-Trapping/Detrapping-Induced Voltage Instability in High- k Gate Dielectrics

    Publication Year: 2012 , Page(s): 152 - 157
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    Investigation of trapping-/detrapping-induced volt- age instabilities does demand not only accurate measurements but also a precise methodology for extracting the exact magnitude of the voltage shifts in the hysteresis curves which is indispensable. Particularly, in dc measurements where the induced voltage shifts are small, an excellent accuracy of the analysis method is required. Therefore, in this paper, we develop a new methodology that, with excellent agreement, models the complete measured Id-Vg hysteresis curves using least squares support vector machines. Furthermore, we apply this model and formulate an optimization problem resulting in the maximum trap-induced voltage shifts in the entire hysteresis curves. Also, for the first time, we quantify the induced error on these extracted maxima. Finally, we illustrate the applicability of the introduced methodology by profiling the initially present and stress-induced defects in a 1-nm SiO2/3-nm HfSiO dielectric stack. View full abstract»

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Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.