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Computers, IEEE Transactions on

Issue 4 • Date April 2012

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2012 , Page(s): c1
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  • [Cover 2]

    Publication Year: 2012 , Page(s): c2
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  • Leveraging a Compound Graph-Based DHT for Multi-Attribute Range Queries with Performance Analysis

    Publication Year: 2012 , Page(s): 433 - 447
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2365 KB) |  | HTML iconHTML  

    Resource discovery is critical to the usability and accessibility of grid computing systems. Distributed Hash Table (DHT) has been applied to grid systems as a distributed mechanism for providing scalable range-query and multi-attribute resource discovery. Multi-DHT-based approaches depend on multiple DHT networks with each network responsible for a single attribute. Single-DHT-based approaches ke... View full abstract»

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  • New Design for Testability Approach for Clock Fault Testing

    Publication Year: 2012 , Page(s): 448 - 457
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    We propose a new design for testability approach for testing clock faults of next generation high performance microprocessors. In fact, it has been shown that conventional manufacturing test is unable to guarantee their detection, although they could compromise the effectiveness of delay fault testing, as well as the microprocessor correct operation in the field. These conditions will of course wo... View full abstract»

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  • Locality-Preserving Clustering and Discovery of Resources in Wide-Area Distributed Computational Grids

    Publication Year: 2012 , Page(s): 458 - 473
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3853 KB) |  | HTML iconHTML  

    In large-scale computational Grids, discovery of heterogeneous resources as a working group is crucial to achieving scalable performance. This paper presents a resource management scheme including a hierarchical cycloid overlay architecture, resource clustering and discovery algorithms for wide-area distributed Grid systems. We establish program/data locality by clustering resources based on their... View full abstract»

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  • An Energy-Efficient Memristive Threshold Logic Circuit

    Publication Year: 2012 , Page(s): 474 - 487
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1164 KB) |  | HTML iconHTML  

    Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, whi... View full abstract»

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  • Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs

    Publication Year: 2012 , Page(s): 488 - 501
    Cited by:  Papers (5)
    Multimedia
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1255 KB) |  | HTML iconHTML  

    The threat of soft error induced system failure in computing systems has become more prominent, as we adopt ultradeep submicron process technologies. In this paper, we propose two efficient soft error mitigation schemes, namely, Soft Error Mitigation (SEM) and Soft and Timing Error Mitigation (STEM), using the approach of multiple clocking of data for protecting combinational logic blocks from sof... View full abstract»

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  • Linear Time Memory Consistency Verification

    Publication Year: 2012 , Page(s): 502 - 516
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (868 KB) |  | HTML iconHTML  

    Verifying the execution of a parallel program against a given memory consistency model (memory consistency verification) is a crucial problem in the functional validation of Chip Multiprocessor (CMP). In the absence of additional information, the above problem is known to be NP-hard. By adopting the pending period information, this paper proposes the first linear-time software-based approach to me... View full abstract»

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  • TRAID: Exploiting Temporal Redundancy and Spatial Redundancy to Boost Transaction Processing Systems Performance

    Publication Year: 2012 , Page(s): 517 - 529
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1150 KB) |  | HTML iconHTML  

    In the past few years, more storage system applications have employed transaction processing techniques to ensure data integrity and consistency. Logging is one of the key requirements to ensure transaction Atomicity, Consistency, Isolation, Durability (ACID) properties and data recoverability in transaction processing systems (TPS). Recently, emerging complex I/O bound transactions have resulted ... View full abstract»

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  • Modeling Energy-Time Trade-Offs in VLSI Computation

    Publication Year: 2012 , Page(s): 530 - 547
    Cited by:  Papers (1)
    Multimedia
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (856 KB) |  | HTML iconHTML  

    The performance of today's computers is limited primarily by power consumption rather than the number of instructions executed. Because the energy required to perform an operation using VLSI circuits drops rapidly with the time allowed for the operation, many slow processors can complete a parallel computation using less time and less energy than a fast uniprocessor that can execute the best seque... View full abstract»

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  • Efficient Runtime Detection and Toleration of Asymmetric Races

    Publication Year: 2012 , Page(s): 548 - 562
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1539 KB) |  | HTML iconHTML  

    We introduce ToleRace, a runtime system that allows programs to detect and even tolerate asymmetric data races. Asymmetric races are race conditions where one thread correctly acquires and releases a lock for a shared variable while another thread improperly accesses the same variable. ToleRace provides approximate isolation in the critical sections of lock-based parallel programs by creating a lo... View full abstract»

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  • Complete System Power Estimation Using Processor Performance Events

    Publication Year: 2012 , Page(s): 563 - 577
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (7398 KB) |  | HTML iconHTML  

    This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. The approach takes advantage of the "trickle-down” effect of performance events in microprocessors. While it has been known that CPU power consumption is correlated to processor performance, the use of well-known performance-related events within a microprocessor s... View full abstract»

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  • On the Computation of Common Test Data for Broadside and Skewed-Load Tests

    Publication Year: 2012 , Page(s): 578 - 583
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1433 KB) |  | HTML iconHTML  

    Skewed-load and broadside tests complement each other and allow higher delay fault coverage to be achieved for a standard-scan circuit that supports both types of tests. The difference between the two types of tests is mainly in the test application process. The input test data required for both of them are similar. This similarity is used in this work to compute compact input test data that can b... View full abstract»

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  • On the Polynomial Multiplication in Chebyshev Form

    Publication Year: 2012 , Page(s): 584 - 587
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    We give an efficient multiplication method for polynomials in Chebyshev form. This multiplication method is different from the previous ones. Theoretically, we show that the number of multiplications is at least as good as Karatsuba-based algorithm. Moreover, using the proposed method, we improve the number of additions slightly. We remark that our method works efficiently for any N and it is easy... View full abstract»

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  • Comment on "DACO: A High Performance Disk Architecture”

    Publication Year: 2012 , Page(s): 588 - 590
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (80 KB) |  | HTML iconHTML  

    DACO is a proposal to provide disk head separation so that a Read-Modify-Write to update check blocks in RAID arrays with erasure encoding can be processed with a minimal rotational delay. Aside from the difficulty associated with implementation of such R/W heads, there are various reasons why such a disk architecture which runs contrary to the write verify SCSI (read after write) command is not h... View full abstract»

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  • Comments on "Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation”

    Publication Year: 2012 , Page(s): 591 - 592
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (109 KB) |  | HTML iconHTML  

    In 2008, Dimitrov et al. proposed a point multiplication algorithm on Koblitz curves using multiple-base expansions. They claimed that their algorithm is the first provably sublinear point multiplication algorithm on Koblitz curves. In this paper, we show that the well-known τ-adic NAF method is already sublinear and also guarantees a better average performance. View full abstract»

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  • [Cover3]

    Publication Year: 2012 , Page(s): c3
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    Freely Available from IEEE
  • [Cover 4]

    Publication Year: 2012 , Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org