By Topic

Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 2 • Date Feb. 2012

Filter Results

Displaying Results 1 - 16 of 16
  • Table of contents

    Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (36 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (39 KB)  
    Freely Available from IEEE
  • On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation

    Page(s): 73 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1033 KB) |  | HTML iconHTML  

    A novel circuit technique that stabilizes the oscillation frequency of a ring-type voltage-controlled oscillator (RVCO) is demonstrated. The technique uses on-chip bias-current and voltage-swing controllers, which compensate RVCO oscillation frequency changes caused by supply noise and process variation. A prototype phase-locked loop (PLL) having the RVCO with the compensation circuit is fabricated with 0.13-μm CMOS technology. At the operating frequency of 4 GHz, the measured PLL rms jitter improves from 20.11 to 5.78 ps with 4-MHz RVCO supply noise. Simulation results show that the oscillation frequency difference between FF and SS corner is reduced from 63% to 6% of the NN corner oscillation frequency. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of mM-W Fully Integrated CMOS Standing-Wave VCOs Using Low-Loss CPW Resonators

    Page(s): 78 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (658 KB) |  | HTML iconHTML  

    The design of two fully integrated 43-GHz voltage-controlled oscillators (VCOs) implemented in a 90-nm CMOS process is presented. Both use standing-wave transmission line resonators instead of a lumped tank to provide extended output frequency ranges and relatively low phase noise (PN). Coplanar waveguide structures with and without slow-wave features were employed in the two VCO circuits. The test results of the manufactured chips were compared. The circuit with the slow-wave feature showed a lower PN (-102.7 dBc/Hz at 1 MHz), whereas the one without the slow-wave structure showed a wider tuning range (1.96 GHz). The two VCOs were developed for use in licensed E-band transceiver systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal Design for Delta–Sigma Modulators With Root Loci Inside Unit Circle

    Page(s): 83 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    Single-stage high-order delta-sigma modulators (DSMs) designed by methods with root loci inside the unit circle (RLiUC) can operate stably with full-scale input. The previously published RLiUC method uses a conservative approach to design the loop filter's transfer function H(z) of a DSM, thus resulting in a modest SNR. In this brief, the pole-zero locations of H(z) are optimized to maximize the stable input range while minimizing SNR reduction. Accordingly, optimal third- and fourth-order RLiUC DSMs are designed, and a systematic method for orders higher than 4 is developed. The considerations for the optimal design are the in-band noise attenuation and out-of-band gain of RLiUC DSMs. With an oversampling ratio of 32 and a quantizer bit number of 6, the optimized fourth-order RLiUC DSM achieves a peak SNR of 109 dB. Compared with the previously published result, the SNR is improved by 20 dB. To demonstrate the advantage of RLiUC DSMs, an application example for a class-D amplifier is used. With the RLiUC DSM, the achieved low-distortion output power of class-D amplifiers can be maximized. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Embedded Analog Nonvolatile Memory With Bidirectional and Linear Programmability

    Page(s): 88 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    Nonvolatile storage of analog values with floating-gate transistors has been useful for many applications. While most proposed analog nonvolatile memory devices employ electron tunneling to modify floating-gate charges, this brief presents an embedded analog nonvolatile memory device that employs only hot-carrier injections to achieve bidirectional programmability. Without using electron tunneling, the proposed circuit not only avoids multiplexing high-voltage signals but also facilitates direct storage of new data. In addition, each memory cell incorporates a simple inverter to make the programming process nearly linear, facilitating bidirectional and linear adaptability for neuromorphic systems. A prototype array of the analog memory has been fabricated with the standard CMOS 0.35- technology. The chip includes a simple on-chip comparator to program the analog memory accurately and automatically by negative feedback. The effective resolution is more than 8 bits over a dynamic range of 1.4 V. The intercell disturbance during programming and the data retention ability are also examined. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A High-Resolution UWB IR Superregenerative Receiver Front End With an SRD Quench Shaper

    Page(s): 93 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB) |  | HTML iconHTML  

    We present a simple receiver front end that makes use of the baseband superregeneration principle to detect ultrawideband (UWB) impulse radio signals. The UWB antenna is directly connected to the core circuit consisting of a resistor-capacitor (RC) network coupled to a negative resistance that varies under the control of an external quench generator. Due to a step-recovery-diode quench shaper, 50-ps time-domain sensitivity windows are generated that filter the received pulses and reject noise and interference. The circuit achieves high gain, exhibits automatic gain control, and directly demodulates binary phase modulations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiplication by Rational Constants

    Page(s): 98 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    Multiplications by simple rational constants often appear in fixed- or floating-point application code, for instance, in the form of division by an integer constant. The hardware implementation of such operations is of practical interest to reconfigurable computing. It is well known that the binary representation of rational constants is eventually periodic. This brief shows how this feature can be exploited to implement multiplication by a rational constant in a number of additions that is logarithmic in the precision. An open-source implementation of these techniques is provided and is shown to be practically relevant for constants with small numerators and denominators, where it provides improvements of 20% to 40% in area with respect to the state of the art. It is also shown that, for such constants, the additional cost for a correctly rounded result is very small and that correct rounding very often comes for free in practice. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine

    Page(s): 103 - 107
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB) |  | HTML iconHTML  

    The differential power analysis (DPA) has become a big threat to crypto chips since it can efficiently disclose the secret key without much effort. Several methods have been proposed in literatures to resist the DPA attack, but they largely increase the hardware cost and severely degrade the throughput. In this brief, a security problem based on ring oscillators is resolved by a new architecture with self-generated true random sequence. The true random-based architecture is implemented with an Advanced Encryption Standard (AES) crypto engine using UMC 90-nm CMOS technology. The DPA-resistant AES engine can achieve 2.97-Gb/s throughput at an operating frequency of 255 MHz with a 0.104- cell area. The proposed DPA countermeasure circuit has only 6.2% area and 18.5% power overhead without throughput degradation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator

    Page(s): 108 - 112
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (909 KB) |  | HTML iconHTML  

    A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3 × (3.5 x) and 3.7 × (5.8 x) power and energy-delay product efficiency, respectively. In addition, the proposed work is 2.7 × faster at iso-energy(80 fJ) or 3.3 × more energy efficient at iso-delay(200 ps) than existing designs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Maximally Flat CIC Compensation Filter: Design and Multiplierless Implementation

    Page(s): 113 - 117
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB) |  | HTML iconHTML  

    This brief introduces a design and implementation of maximally flat cascaded integrator comb compensation filters. In particular, we consider second- and fourth-order linear phase filters for narrow-band and wideband compensation. Closed-form equations for the computation of the filter coefficients are given. The multiplierless implementation is also considered. The number of adders is a function of the decimation factor Dand the number of stages N. The implementation complexity is discussed, and comparisons with some methods reported in the literature are provided. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A New Design Method of the Starting Block in Lattice Structure of Arbitrary-Length Linear Phase Paraunitary Filter Bank by Combining Two Polyphase Matrices

    Page(s): 118 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    Constructing the starting block is the core of designing an arbitrary-length linear phase paraunitary filter bank (ALLPPUFB), and lattice structure is an efficient approach of ALLPPUFB design. This brief proposes a new ALLPPUFB starting block design by combining two polyphase matrices of constrained-length linear phase paraunitary filter bank. The proposed design is much easier to be understood than existing ones due to the brief design process. Moreover, it might be modified and used for unaddressed topics in neighboring fields, such as starting block design for arbitrary-length oversampled linear phase paraunitary filter bank. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Note on Observers for Discrete-Time Lipschitz Nonlinear Systems

    Page(s): 123 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    This brief considers observer design for a class of discrete-time nonlinear systems with Lipschitz nonlinearities. We first remark some statements and results in a recent brief by Zemouche and Boutayeb. In particular, we show that their results are more conservative than an existing one, rather than less conservative as claimed. Moreover, most of the existing results are only applicable to some particular classes of Lipschitz systems with a Lipschitz constant less than one. In order to obtain less conservative results, the concept of a one-sided Lipschitz condition, which is an extension of its well-known Lipschitz counterpart, is introduced. Sufficient conditions ensuring the existence of state observers for one-sided Lipschitz nonlinear systems are then presented. A numerical example is included to illustrate the advantages and effectiveness of the proposed design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DDCSK-Walsh Coding: A Reliable Chaotic Modulation-Based Transmission Technique

    Page(s): 128 - 132
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    To overcome the performance loss of noncoherent detectors of differential chaos-shift keying (DCSK), some improved versions of DCSK have been proposed. However, little has been done to improve the multiuser DCSK system based on Walsh codes (WCs), i.e., referred to as DCSK-WC, although it is considered more feasible in practice among the existing multiuser DCSK systems. This brief introduces a novel differentially DCSK (DDCSK) technique into such a multiuser system so as to build the desirable DDCSK-WC, obtaining significant performance gain, as compared with the conventional DCSK-WC, while retaining its hardware complexity unchanged. Moreover, the proposed system can greatly enhance the robustness against intersymbol interference in a wireless multipath fading channel. Therefore, the new system is deemed to provide a good alternative transmission scheme for wireless communication based on chaotic modulation, in such as indoor applications of the transmitted-reference ultrawideband. The theoretical analysis and simulated noise performances of the proposed system demonstrate their high consistence. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Circuits and Systems Society Information

    Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (32 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

    Page(s): C4
    Save to Project icon | Request Permissions | PDF file iconPDF (33 KB)  
    Freely Available from IEEE

Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope