Issue 1 • Date January 2012
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Displaying Results 1 - 7 of 7
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Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles
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PDF (605 KB)
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Design and evaluation of variable stages pipeline processor with low-energy techniques
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PDF (645 KB)
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Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures
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PDF (670 KB)
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Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
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PDF (1141 KB)


