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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 8 • Date Aug 1993

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Displaying Results 1 - 15 of 15
  • On clustering for maximal regularity extraction

    Publication Year: 1993 , Page(s): 1198 - 1208
    Cited by:  Papers (20)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB)  

    The authors point out that proper usage of regularity in digital systems leads to efficient as well as economical designs. This important question of regularity extraction is examined, and a general and efficient methodology for component clustering based on the concept of structural regularity is presented. While the concept of regularity can be employed to simplify many problems in the area of design automation, system- and logic-level applications are emphasized here. The authors show how identifying clusters in a circuit can simplify two important CAD problems-system-level clustering and module (layout) generation. A prototype system based on these ideas has been built, and some real-life examples are considered for testing. The results are encouraging; they demonstrate the essential role such a system could play in aiding the high-level system designer. Research is under way to explore some of the other promising applications that such a system could have View full abstract»

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  • Automatic grid refinement and higher order flux discretization for diffusion modeling

    Publication Year: 1993 , Page(s): 1209 - 1216
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    The authors point out that modern numerical process simulators are becoming increasingly complicated in both physical models and domain shape. Grid generation is difficult for these simulators because of the inherently transient nature of the problems being solved. Here, adaptive grid refinement is considered for use in solving diffusion problems. Higher order approximations to the discretized diffusion flux are also studied. Several methods of both adaptive grid refinement and discretization are investigated and compared in terms of CPU time and final discretization error. All the methods are directly applied to the one-dimensional version of SUPREM-IV View full abstract»

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  • Automated design management using traces

    Publication Year: 1993 , Page(s): 1077 - 1095
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1792 KB)  

    An automatic management system for CAD based on the idea that CAD tools can leave a trace of their execution is proposed. The trace, represented as a bipartite directed and acyclic graph in which the nodes represent either design data or tool invocations, is both a record of the design activity and a graph representing the dependencies among the design objects. The architecture of the proposed system is distributed. A server manages the trace, while a number of clients can concurrently interact with the trace through the server. The system is nonintrusive, because it does not affect the way designers interact with the tools. The design manager has been implemented in a system called VOV, which has been tested View full abstract»

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  • SALSA: a new approach to scheduling with timing constraints

    Publication Year: 1993 , Page(s): 1107 - 1122
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1484 KB)  

    An approach to scheduling in high-level synthesis that meets timing constraints while attempting to minimize hardware resource costs is described. The approach is based on a modified control/data-flow graph (CDFG) representation called SALSA. SALSA provides a simple move set that allows alternative schedules to be quickly explored while maintaining timing constraints. It is shown that this move set is complete in that any legal schedule can be reached using some sequence of move applications. In addition, SALSA provides support for scheduling with conditionals, loops, and subroutines. Scheduling with SALSA is performed in two steps. First, an initial schedule that meets timing constraints is generated using a constraint solution algorithm adapted from layout compaction. Second, the schedule is improved using the SALSA move set under control of a simulated annealing algorithm. Results show the scheduler's ability to find good schedules which meet timing constraints in reasonable execution times View full abstract»

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  • Scan-based transition test

    Publication Year: 1993 , Page(s): 1232 - 1241
    Cited by:  Papers (88)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the one that launches the transition) is required to be the next (i.e., one-bit-shift) pattern in the scan chain. Although a skewed-load transition test is attractive from a timing point of view, there are various problems that may arise if this strategy is used. Here, several issues of skewed-load transition test are investigated. Issues such as transition test calculus, detection probability of transition faults, transition fault coverage, and enhancement of transition test quality are thoroughly studied View full abstract»

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  • Interaction semantics of a symbolic layout editor for parameterized modules

    Publication Year: 1993 , Page(s): 1096 - 1106
    Cited by:  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    An interactive graphical editor for parameterized layout generators, based on symbolic layout, is discussed. One basic idea is to have built-in rules, corresponding to basic knowledge about elementary things in VLSI design, in order to make the tool behave as an experienced partner to the designer. It was found that the fundamental problem was not to implement but to select a proper set of rules to define the semantics of the tool. The problem was attacked by actually implementing various experimental versions and using them to create layout. These experiments and the conclusions are summarized. For example, the fundamental importance of proper mechanisms to explicitly express geometrical constraints, such as pitch-matching, is shown. It is also shown how parameterization can be introduced in a user-friendly and natural way through the graphical, symbolic layout view View full abstract»

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  • STOIC: state assignment based on output/input functions

    Publication Year: 1993 , Page(s): 1123 - 1131
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    A finite-state-machine (FSM) synthesis procedure, specifically aimed at using primary inputs and primary output functions as state variables, is proposed. The number of next-state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also, as more of the state variables are directly observable (the primary outputs used as state variables), and directly controllable (the primary inputs used as state variables) the testability of the implementation is increased. Experimental results are given to demonstrate the effectiveness of the procedure in reducing area View full abstract»

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  • Drift reliability optimization in IC design: generalized formulation and practical examples

    Publication Year: 1993 , Page(s): 1242 - 1252
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    A generalized formulation of the drift reliability optimization problem is presented. Algorithmic solutions are also proposed. They can be implemented readily in the existing circuit optimization environments and applied to integrated circuit design. Such applications are demonstrated, considering degradations due to hot electron effects. The results show that the proposed approach can significantly increase long-term circuit reliability and increase its robustness View full abstract»

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  • Delay-fault test generation and synthesis for testability under a standard scan design methodology

    Publication Year: 1993 , Page(s): 1217 - 1231
    Cited by:  Papers (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1368 KB)  

    The problems of test generation and synthesis aimed at producing VLSI sequential circuits that are delay-fault testable under a standard scan design methodology are considered. Theoretical results regarding the standard scan-delay testability of finite state machines (FSMs) described at the state transition graph (STG) level are given. It is shown that a one-hot coded and optimized FSM whose STG satisfies a certain property is guaranteed to be fully gate-delay-fault testable under standard scan. This result is extended to arbitrary-length encodings, and a heuristic state assignment algorithm that results in highly gate-delay-fault testable sequential FSMs is developed. The authors also consider the problem of delay test generation for large sequential circuits and modify a PODEM-based combinational test pattern generator. The modifications involve a two-time-frame expansion of the combinational logic of the circuit and the use of backtracking heuristics tailored for the problem. A version of the scan shifting technique is also used in the test pattern generator. Test generation, flip-flop ordering, flip-flop selection and test set compaction results on large benchmark circuits are presented View full abstract»

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  • Post-layout timing simulation of CMOS circuits

    Publication Year: 1993 , Page(s): 1170 - 1177
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    As a necessary aid to system integration, the authors present the implementation and performance of a pattern-dependent timing simulator, PATH-RUNNER. Organized around an explicit formulation of delays, this is an event-driven simulator which processes only transitions with gates controlled by events. Extraction of conduction paths from a general decomposition of data paths in unidirectional blocks allows general conflictual situations to be solved. Configuration problems detected during the evaluation, such as pulse rejection and strength conflicts, are illustrated, and effective solutions of conflictual configurations are given. It is shown that the implementation of a two-pass algorithm results in a significant improvement of speed. Execution times have been found to be nearly linear with the node numbers. Comparison of simulation times obtained from other timing simulators is given. SPICE compatibilities of PATH-RUNNER allow automatic real characterization of data paths from post-layout extracted net lists, with SPICE-like accuracy for evaluation of delays on real structures View full abstract»

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  • Area routing for analog layout

    Publication Year: 1993 , Page(s): 1186 - 1197
    Cited by:  Papers (19)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1072 KB)  

    An area router specifically tailored for the layout of analog circuits is presented. It is based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable cost function based on a set of user-defined weights. The weights can be automatically defined based on high-level electrical performance specifications and determine the net scheduling. An algorithm for symmetric routing preserves symmetries in differential architectures. Different current paths can be dealt with in each wire by means of a net partitioning procedure driven by information on the current driven by terminals. Shields can be built between critically coupled wires, in order to guarantee an effective limitation of cross-coupling. The weight-driven programmable cost function makes this router particularly suitable for a performance-driven approach to analog routing. Automatic weight definition also makes the use of the tool independent of the user's expertise. The implemented algorithms are described, and results proving the effectiveness of this approach are given View full abstract»

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  • An efficient algorithm for some multirow layout problems

    Publication Year: 1993 , Page(s): 1178 - 1185
    Cited by:  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    Three multirow layout problems are presented: transistor orientation, contact positioning and symbolic-to-shape translation. It is shown that these multirow problems have a common property, called quantitative dependency. Using this property, an optimization technique which is based on a penalty-delay strategy is presented. It is proved that the penalty-delay strategy assures optimality, and that the optimal solution can be obtained in linear time. The algorithmic approach is based on the observation that optimal layout decisions in any region within a cell or a macro depend only on quantitative measures of the decisions in other regions, rather than on their details. This suggests a departure from the traditional approach of handling the different regions separately and combining them afterward into a single unit, an approach that may degrade the quality of the final layout. Instead, the entire macro can be processed at once, taking into account the mutual quantitative dependency between distinguished regions View full abstract»

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  • Synchronization of pipelines

    Publication Year: 1993 , Page(s): 1132 - 1146
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1056 KB)  

    A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization View full abstract»

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  • Matching-based methods for high-performance clock routing

    Publication Year: 1993 , Page(s): 1157 - 1169
    Cited by:  Papers (23)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    The authors point out that minimizing clock skew is important in the design of high-performance VLSI systems. A general clock routing scheme that achieves extremely small clock skews while still using a reasonable amount of wirelength is presented. The routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of the clock routing tree is on average within a constant factor of the wirelength in an optimal Steiner tree, and in the worst case is bounded by O(√l 1l2×1√n) for n terminals arbitrarily distributed in the l1×l2 grid. The bottom-up construction readily extends to general cell layouts, where it also achieves essentially zero clock skew within reasonably bounded total wirelength. The algorithms have been tested on numerous random examples and also on layouts of industrial benchmark circuits. The results are very promising: the clock routing yields near-zero average clock skew while using total wirelength competitive with that used by previously known methods View full abstract»

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  • On the circuit implementation problem

    Publication Year: 1993 , Page(s): 1147 - 1156
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB)  

    The authors consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, the basic circuit implementation problem and the general circuit implementation problem, are shown to be NP-hard. A pseudo-polynomial-time algorithm for the basic circuits is developed, and heuristics for the basic circuit implementation problem on general circuits are formulated and experimented with View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu