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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Date Aug 1993

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Displaying Results 1 - 15 of 15
  • Interaction semantics of a symbolic layout editor for parameterized modules

    Publication Year: 1993, Page(s):1096 - 1106
    Cited by:  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    An interactive graphical editor for parameterized layout generators, based on symbolic layout, is discussed. One basic idea is to have built-in rules, corresponding to basic knowledge about elementary things in VLSI design, in order to make the tool behave as an experienced partner to the designer. It was found that the fundamental problem was not to implement but to select a proper set of rules t... View full abstract»

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  • Synchronization of pipelines

    Publication Year: 1993, Page(s):1132 - 1146
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pi... View full abstract»

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  • Drift reliability optimization in IC design: generalized formulation and practical examples

    Publication Year: 1993, Page(s):1242 - 1252
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    A generalized formulation of the drift reliability optimization problem is presented. Algorithmic solutions are also proposed. They can be implemented readily in the existing circuit optimization environments and applied to integrated circuit design. Such applications are demonstrated, considering degradations due to hot electron effects. The results show that the proposed approach can significant... View full abstract»

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  • STOIC: state assignment based on output/input functions

    Publication Year: 1993, Page(s):1123 - 1131
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    A finite-state-machine (FSM) synthesis procedure, specifically aimed at using primary inputs and primary output functions as state variables, is proposed. The number of next-state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also, as more of the state variables are directly observable (the primary outputs used as state variables),... View full abstract»

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  • On the circuit implementation problem

    Publication Year: 1993, Page(s):1147 - 1156
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    The authors consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, the basic circuit implementation problem and the general circuit implementation problem, are shown to be NP-hard. A pseudo-polynomial-time algorithm for the basic cir... View full abstract»

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  • Area routing for analog layout

    Publication Year: 1993, Page(s):1186 - 1197
    Cited by:  Papers (22)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    An area router specifically tailored for the layout of analog circuits is presented. It is based on the A* algorithm, which combines the flexibility of maze routing with computational efficiency. Parasitics are controlled by means of a programmable cost function based on a set of user-defined weights. The weights can be automatically defined based on high-level electrical performance spec... View full abstract»

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  • Post-layout timing simulation of CMOS circuits

    Publication Year: 1993, Page(s):1170 - 1177
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    As a necessary aid to system integration, the authors present the implementation and performance of a pattern-dependent timing simulator, PATH-RUNNER. Organized around an explicit formulation of delays, this is an event-driven simulator which processes only transitions with gates controlled by events. Extraction of conduction paths from a general decomposition of data paths in unidirectional block... View full abstract»

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  • Matching-based methods for high-performance clock routing

    Publication Year: 1993, Page(s):1157 - 1169
    Cited by:  Papers (26)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB)

    The authors point out that minimizing clock skew is important in the design of high-performance VLSI systems. A general clock routing scheme that achieves extremely small clock skews while still using a reasonable amount of wirelength is presented. The routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of the clock ... View full abstract»

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  • Automated design management using traces

    Publication Year: 1993, Page(s):1077 - 1095
    Cited by:  Papers (8)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1792 KB)

    An automatic management system for CAD based on the idea that CAD tools can leave a trace of their execution is proposed. The trace, represented as a bipartite directed and acyclic graph in which the nodes represent either design data or tool invocations, is both a record of the design activity and a graph representing the dependencies among the design objects. The architecture of the proposed sys... View full abstract»

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  • Scan-based transition test

    Publication Year: 1993, Page(s):1232 - 1241
    Cited by:  Papers (101)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    Skewed-load transition test is a form of scan-based transition test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector ... View full abstract»

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  • On clustering for maximal regularity extraction

    Publication Year: 1993, Page(s):1198 - 1208
    Cited by:  Papers (26)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    The authors point out that proper usage of regularity in digital systems leads to efficient as well as economical designs. This important question of regularity extraction is examined, and a general and efficient methodology for component clustering based on the concept of structural regularity is presented. While the concept of regularity can be employed to simplify many problems in the area of d... View full abstract»

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  • An efficient algorithm for some multirow layout problems

    Publication Year: 1993, Page(s):1178 - 1185
    Cited by:  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Three multirow layout problems are presented: transistor orientation, contact positioning and symbolic-to-shape translation. It is shown that these multirow problems have a common property, called quantitative dependency. Using this property, an optimization technique which is based on a penalty-delay strategy is presented. It is proved that the penalty-delay strategy assures optimality, and that ... View full abstract»

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  • Delay-fault test generation and synthesis for testability under a standard scan design methodology

    Publication Year: 1993, Page(s):1217 - 1231
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1368 KB)

    The problems of test generation and synthesis aimed at producing VLSI sequential circuits that are delay-fault testable under a standard scan design methodology are considered. Theoretical results regarding the standard scan-delay testability of finite state machines (FSMs) described at the state transition graph (STG) level are given. It is shown that a one-hot coded and optimized FSM whose STG s... View full abstract»

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  • Automatic grid refinement and higher order flux discretization for diffusion modeling

    Publication Year: 1993, Page(s):1209 - 1216
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    The authors point out that modern numerical process simulators are becoming increasingly complicated in both physical models and domain shape. Grid generation is difficult for these simulators because of the inherently transient nature of the problems being solved. Here, adaptive grid refinement is considered for use in solving diffusion problems. Higher order approximations to the discretized dif... View full abstract»

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  • SALSA: a new approach to scheduling with timing constraints

    Publication Year: 1993, Page(s):1107 - 1122
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1484 KB)

    An approach to scheduling in high-level synthesis that meets timing constraints while attempting to minimize hardware resource costs is described. The approach is based on a modified control/data-flow graph (CDFG) representation called SALSA. SALSA provides a simple move set that allows alternative schedules to be quickly explored while maintaining timing constraints. It is shown that this move se... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu