# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Displaying Results 1 - 21 of 21

Publication Year: 2012, Page(s): C1
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2012, Page(s): C2
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• ### Guest Editorial Special Section on the 2011 International Symposium on Physical Design

Publication Year: 2012, Page(s):165 - 166
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• ### E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters

Publication Year: 2012, Page(s):167 - 179
Cited by:  Papers (16)
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Electronic beam lithography (EBL) is one of the promising emerging technologies in the sub-22 nm regime. In EBL, the desired circuit patterns are directly shot into the wafer, which overcomes the diffraction limit of light in the current optical lithography system. However, the low throughput becomes its key technical hurdle. In the conventional EBL system, each rectangle in the layout will be pro... View full abstract»

• ### Power-Driven Flip-Flop Merging and Relocation

Publication Year: 2012, Page(s):180 - 191
Cited by:  Papers (15)  |  Patents (1)
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We propose a power-driven flip-flop (FF) merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption while controlling the switching power of the nets connected to the FFs by selectively merging FFs into multibit FFs and relocating them under timin... View full abstract»

• ### INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving

Publication Year: 2012, Page(s):192 - 204
Cited by:  Papers (21)  |  Patents (1)
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Clock power is the major contributor to dynamic power for modern integrated circuit design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering several such cells and forming a multibit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, and can even save the clock network power and faci... View full abstract»

• ### Obstacle-Aware Clock-Tree Shaping During Placement

Publication Year: 2012, Page(s):205 - 216
Cited by:  Papers (6)
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Traditional integrated circuit (IC) design flows optimize clock networks before signal-net routing are limited by the quality of register placement. Existing publications also reflect this bias and focus mostly on clock routing. The few known techniques for register placement exhibit significant limitations and do not account for recent progress in large-scale placement and obstacle-aware clock-ne... View full abstract»

• ### Integrated Clock Mesh Synthesis With Incremental Register Placement

Publication Year: 2012, Page(s):217 - 227
Cited by:  Papers (6)
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A clock mesh planning and synthesis method is proposed which significantly reduces the power dissipation on the network while considering the power density and timing slack simultaneously. The proposed method is performed at the postplacement stage and consists of three major steps: 1) feasible moving region construction of each register considering timing slack; 2) mesh grid wire generation and p... View full abstract»

• ### Assembling 2-D Blocks Into 3-D Chips

Publication Year: 2012, Page(s):228 - 241
Cited by:  Papers (18)
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Despite numerous advantages of 3-D integrated circuits (ICs), their commercial success remains limited. In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2-D ICs and proven through repeated use. Block-based design reuse is imperative for heterogeneous 3-D ICs where memory, logic, analog, and microelectromechanical systems dies are manufact... View full abstract»

• ### Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips

Publication Year: 2012, Page(s):242 - 254
Cited by:  Papers (7)
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The number of independent input pins used to control the electrodes in digital microfluidic “biochips” is an important cost-driver in the emerging market place, especially for disposable PCB devices that are being developed for clinical and point-of-care diagnostics. However, most prior work on pin-constrained biochip design considers droplet routing and the assignment of pins to ele... View full abstract»

• ### Postgrid Clock Routing for High Performance Microprocessor Designs

Publication Year: 2012, Page(s):255 - 259
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Designing a high-quality clock network is very important in very large-scale integrated designs today, as it is the clock network that synchronizes all the elements of a chip, and it is also a major source of power dissipation of a system. Early study by Pham in 2006 shows that about 18.1% of the total clock capacitance was due to this postgrid clock routing (i.e., lower mesh wires plus clock twig... View full abstract»

• ### Logic Restructuring Using Node Addition and Removal

Publication Year: 2012, Page(s):260 - 270
Cited by:  Papers (7)
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This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing the replaced node. Previous node-merging techniques focus on replacing one node with an existing node in a circuit, but fail to replace a node that has no substitute node. To enhance the node-merging techniques on logic re... View full abstract»

• ### Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Publication Year: 2012, Page(s):271 - 284
Cited by:  Papers (6)
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With lower supply voltages, increased integration densities and higher operating frequencies, power grid verification has become a crucial step in the very large-scale integration design cycle. The accurate estimation of maximum instantaneous power dissipation aims at finding the worst-case scenario where excessive simultaneous switching could impose extreme current demands on the power grid. This... View full abstract»

• ### Correctly Modeling the Diagonal Capacity in Escape Routing

Publication Year: 2012, Page(s):285 - 293
Cited by:  Papers (5)
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Escape routing for packages and printed circuit boards (PCBs) has been studied extensively in the past. Network flow is pervasively used to model this problem. However, none of the previous works correctly models the diagonal capacity, which is essential for 45° routing in most packages and PCBs. As a result, existing algorithms may either produce routing solutions that violate the diagonal... View full abstract»

• ### On the Impact of Within-Die Process Variation in GALS-Based NoC Performance

Publication Year: 2012, Page(s):294 - 307
Cited by:  Papers (4)
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Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at desi... View full abstract»

• ### Physically-Aware $N$ -Detect Test

Publication Year: 2012, Page(s):308 - 321
Cited by:  Papers (1)
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Physically-aware N-detect (PAN-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate PAN-detect tests for large industrial designs. Compared to traditional N-detect test, the quality resulting from PAN-detect is enhanced without any increase in test execution cost. E... View full abstract»

• ### Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences

Publication Year: 2012, Page(s):322 - 326
Cited by:  Papers (1)
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When a multipattern scan-based test is applied at-speed to detect delay defects, it is necessary to change the primary input vectors at-speed. However, tester limitations can make this infeasible. The solution where the primary input vectors are held constant during the test reduces the fault coverage. An alternative solution is to store the primary input sequences of a multipattern test set on-ch... View full abstract»

• ### Errata to “Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010” [Jan 12 61-74]

Publication Year: 2012, Page(s): 327
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Due to a production error, in the above titled paper (ibid., vol. 31, no. 1, pp. 61-74, Jan. 2012), the title appeared incorrectly. The correct title should read "Accelerating FPGA Routing Through Parallelization and Engineering Enhancements." View full abstract»

Publication Year: 2012, Page(s): 328
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2012, Page(s): C3
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

Publication Year: 2012, Page(s): C4
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## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu