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Computers, IEEE Transactions on

Issue 8 • Date Aug 1993

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Displaying Results 1 - 17 of 17
  • On the lower bound to the VLSI complexity of number conversion from weighted to residue representation

    Publication Year: 1993 , Page(s): 962 - 967
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    A lower bound AT2=Ω(n2 ) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns View full abstract»

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  • Signed digit representations of minimal Hamming weight

    Publication Year: 1993 , Page(s): 1007 - 1010
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    The authors give an online algorithm for computing a canonical signed digit representation of minimal Hamming weight for any integer n. Using combinatorial techniques, the probability distributions Pr[Kr=h], where Kr is taken to be a random variable on the uniform probability space of k-digit integers is computed. Also, using a Markov chain analysis, it is shown that E(Kr)~(r-1)k /(r+1) as k→∞ View full abstract»

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  • Fault injection and dependability evaluation of fault-tolerant systems

    Publication Year: 1993 , Page(s): 913 - 923
    Cited by:  Papers (68)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    The authors describe a dependability evaluation method based on fault injection that establishes the link between the experimental evaluation of the fault tolerance process and the fault occurrence process. The main characteristics of a fault injection test sequence aimed at evaluating the coverage of the fault tolerance process are presented. Emphasis is given to the derivation of experimental measures. The various steps by which the fault occurrence and fault tolerance processes are combined to evaluate dependability measures are identified and their interactions are analyzed. The method is illustrated by an application to the dependability evaluation of the distributed fault-tolerant architecture of the Esprit Delta-4 Project View full abstract»

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  • Some fundamental properties of multiple-valued Kleenean functions and determination of their logic formulas

    Publication Year: 1993 , Page(s): 950 - 961
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB)  

    Multiple-valued Kleenean functions that are models of a Kleene algebra and are logic functions expressed by logic formulas composed of variables, constants, and logic operations AND OR, and NOT are discussed. The set of Kleenean functions, is a model with the largest number of logic functions among existing models of a Kleene algebra, such as fuzzy logic functions, regular ternary logic functions, and B-ternary logic functions. Mainly, it is shown that any p-valued Kleenean function is derived from a monotonic ternary input functions and any p-valued unate function is derived from a unate binary input function. The mapping relations between them and the method to determine the logic formula of the Kleenean function and unate function from that of the monotonic ternary input function and unate binary input function, respectively, are classified. 7-or-less-valued Kleenean functions and unate functions of 3-or-fewer variables are enumerated. It is known that the number of p-valued Kleenean functions increases stepwise and that of unate functions increases smoothly as p becomes larger View full abstract»

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  • Embedding of cycles in arrangement graphs

    Publication Year: 1993 , Page(s): 1002 - 1006
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    Arrangement graphs have been proposed as an attractive interconnection topology for large multiprocessor systems. The authors study these graphs by proving the existence of Hamiltonian cycles in any arrangement graph. They also prove that an arrangement graph contains cycles of all lengths ranging between 3 and the size of the graph. They show that an arrangement graph can be decomposed into node disjoint cycles in many different ways View full abstract»

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  • Test-pattern generation based on Reed-Muller coefficients

    Publication Year: 1993 , Page(s): 968 - 980
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1020 KB)  

    Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented View full abstract»

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  • Multiprocessor fault diagnosis under local constraints

    Publication Year: 1993 , Page(s): 984 - 988
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    The authors study the fault diagnosis of multiprocessor systems when fault constraints in the local domain of each processor are specified. They use the comparison-based model. A multiprocessor system S is t-in-L diagnosable if, given a syndrome, all faulty processors can be uniquely identified provided there are at most t faulty processors in the local domain L(u i) ∪ {ui} of every processor, ui in S, where L (ui ) denotes the set of processors adjacent to ui. Certain basic results that lead to efficient conditions for unique diagnosis of a system when certain fault constraints are satisfied in the local domain of each processor in the system are presented. The t-in-L diagnosability of certain regular interconnected systems is examined under the assumption that less than half of the processors in the system are faulty. Diagnosis algorithms for these systems are presented View full abstract»

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  • Novel totally self-checking Berger code checker designs based on generalized Berger code partitioning

    Publication Year: 1993 , Page(s): 1020 - 1024
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Totally self-checking (TSC) Berger code checker designs are presented. The generalized Berger check partitioning is derived. It is proven that a TSC Berger code checker can be constructed from a TSC m-out-of-n checker. For a TSC Berger code checker design, no two-output checker exists for information length 2r-1 , for any positive nonzero r. The presented approach solves this open problem View full abstract»

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  • Generalized Hopfield neural network for concurrent testing

    Publication Year: 1993 , Page(s): 898 - 912
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1104 KB)  

    The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how, by using spectral techniques based on the Reed-Muller transform, the aliasing probability can be expressed as a function of the Reed-Muller coefficients. Therefore, obtaining the checking circuitry means selecting a set of Reed-Muller spectral coefficients, with fewer elements than a given bound, that minimizes the aliasing probability. To apply the neural networks to design the checking circuitry for concurrent testing, the aliasing probability has been used as an energy function, and the Hopfield neural network has been modified to have an associated energy function with any type of polynomial dependence on the processor states View full abstract»

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  • A dynamic programming algorithm for cache memory partitioning for real-time systems

    Publication Year: 1993 , Page(s): 997 - 1001
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    An algorithm for optimally partitioning two-level memory systems for deterministic, real-time performance is presented. The algorithm finds the optimal solution in polynomial time, which supports on-line reconfiguration of memory resources in response to changing requirements View full abstract»

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  • Scattering and gathering messages in networks of processors

    Publication Year: 1993 , Page(s): 938 - 949
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1128 KB)  

    The operations of scattering and gathering in a network of processors involve one processor of the network (P0) communicating with all other processors. In scattering, P0 sends distinct messages to P0. The authors consider networks that are trees of processors. Algorithms for scattering messages from and gathering messages to the processor that resides at the root of the tree are presented. The algorithms are quite general, in that the messages transmitted can differ arbitrarily in length; quite strong, in that they send messages along noncolliding paths, and hence do not require any buffering or queueing mechanisms in the processors; and quite efficient in that algorithms for scattering in general trees are optimal, the algorithm for gathering in a path is optimal and the algorithms for gathering in general trees are nearly optimal. The algorithms can easily be converted using spanning trees to efficient algorithms for scattering and gathering in networks of arbitrary topologies View full abstract»

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  • A multiclass priority-based slotted-ring LAN and its analysis

    Publication Year: 1993 , Page(s): 1015 - 1020
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    A protocol for a slotted-ring local area network to handle two classes of jobs in which one class has preemptive priority over the other is presented. The detailed response time distribution analysis for different classes of jobs is given. It is shown that the modeling and analysis can be extended to multiclass jobs View full abstract»

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  • Diagnosability and diagnosis of algorithm-based fault-tolerant systems

    Publication Year: 1993 , Page(s): 924 - 937
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1252 KB)  

    Parallel processing architectures are commonly used for signal processing and other computationally intensive applications. These applications are characterized by high throughput and long processing periods. Such characteristics decrease the reliability of high-performance architectures. The erroneous data produced by faulty processors could have damaging consequences, particularly in critical real-time applications. It is therefore desirable that any erroneous data produced by the system be detected and located as quickly as possible. Algorithm-based fault tolerance (ABFT) is a low-cost system-level concurrent error detection and fault location scheme. Methods used in the analysis of multiprocessor systems using system-level diagnosis are applied to the analysis of ABFT systems. A new algorithm for analyzing an ABFT system for its fault diagnosability is developed using these methods. Based on this work, a fault diagnosis algorithm is developed for ABFT systems View full abstract»

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  • A data structure for circular string analysis and visualization

    Publication Year: 1993 , Page(s): 992 - 997
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    A csdawg for circular strings, which is obtained by making simple modifications to the compact symmetric directed acyclic word graph (csdawg) for linear strings, is proposed. This data structure does not contain extraneous vertices and, consequently, avoids the disadvantages of previous methods. Using this method, algorithms which make use of the csdawg for linear strings can then be extended to circular strings with trivial modifications. The extended algorithms continue to have the same time and space complexities. Moreover, the extensions take the form of postprocessing or preprocessing steps which are simple to add on to a system built for linear strings, particularly in an object-oriented language View full abstract»

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  • On computing multiplicative inverses in GF(2m)

    Publication Year: 1993 , Page(s): 1010 - 1015
    Cited by:  Papers (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    The design of a modular standard basis inversion for Galois fields GF(2m) based on Euclid's algorithm for computing the greatest common divisor of two polynomials is presented. The asymptotic complexity is linear with m both in computation time and area requirement, thus resulting in an AT-complexity of O( m2). This is a significant improvement over the best previous proposal which achieves AT-complexity of only O (m3) View full abstract»

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  • On single-fault set diagnosability in the PMC model

    Publication Year: 1993 , Page(s): 981 - 983
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A. Somani et al, (1987) introduced the single-fault set diagnosability measure and gave an O(n3.5) algorithm for determining it in the PMC model. The authors present a new algorithm for the same problem with a time complexity of only O(n2.5) View full abstract»

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  • Geometrical learning algorithm for multilayer neural networks in a binary field

    Publication Year: 1993 , Page(s): 988 - 992
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A geometrical expansion learning algorithm for multilayer neural networks using unipolar binary neurons with integer connection weights, which guarantees convergence for any Boolean function, is introduced. Neurons in the hidden layer develop as necessary without supervision. In addition, the computational amount is much less than that of the backpropagation algorithm View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org