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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • Date June 1993

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Displaying Results 1 - 16 of 16
  • Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays

    Publication Year: 1993, Page(s):224 - 228
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (479 KB)

    A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentiall... View full abstract»

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  • Design and analysis of defect tolerant hierarchical sorting networks

    Publication Year: 1993, Page(s):219 - 223
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (585 KB)

    A hierarchical modular sorting network which achieves a balance in area-time cost between the odd-even transposition sort and the bitonic sort is presented. It consumes less hardware than a single-level odd-even sorter and reduces the wire complexity of the bitonic sorter in VLSI or WSI (wafer-scale integration) implementation. The optimal number of levels in the hierarchy is evaluated, and the so... View full abstract»

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  • A design of a fast and area efficient multi-input Muller C-element

    Publication Year: 1993, Page(s):215 - 219
    Cited by:  Papers (26)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection in self-timed circuits. An n-input Muller C-element design which uses the multilevel logic design technique and has a symmetric format for any integer n >or=2 is presented. In comparison with series-parallel MOS structure implementations and C-element tree implementations, the presen... View full abstract»

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  • MARVLE: a VLSI chip for data compression using tree-based codes

    Publication Year: 1993, Page(s):203 - 214
    Cited by:  Papers (26)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1354 KB)

    Describes the architecture and design of a CMOS VLSI chip for data compression and decompression using tree-based codes. The chip, called MARVLE, implements a memory-based architecture for variable length encoding and decoding based on tree-based codes. The architecture is based on an efficient scheme of mapping the tree representing any binary code onto a memory device. A prototype 2-mm CMOS VLSI... View full abstract»

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  • VLSI architectures for discrete wavelet transforms

    Publication Year: 1993, Page(s):191 - 202
    Cited by:  Papers (215)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1007 KB)

    A folded architecture and a digit-serial architecture are proposed for implementation of one- and two-dimensional discrete wavelet transforms. In the one-dimensional folded architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded architecture is minimized by the use of a generalized life time analysis. The con... View full abstract»

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  • Estimating architectural resources and performance for high-level synthesis applications

    Publication Year: 1993, Page(s):175 - 190
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1604 KB)

    The authors present a solution to the following problems related to architectural synthesis. (1) Given an input specification and a performance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. (2) Determine a lower bound performance for executing an input specification for a given ... View full abstract»

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  • An efficient logic emulation system

    Publication Year: 1993, Page(s):171 - 174
    Cited by:  Papers (55)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded int... View full abstract»

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  • The selective extra stage butterfly

    Publication Year: 1993, Page(s):167 - 171
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    Multistage interconnection networks (MINs) have been used extensively as communication networks in parallel machines due to their high bandwidth, low diameter and constant degree switches. The fault-tolerance of multistage networks can be improved by simply adding extra stages to the network. A novel method of attaching the extra stages in MINs so that they are used in the absence of faults but no... View full abstract»

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  • Modified Booth algorithm for high radix fixed-point multiplication

    Publication Year: 1993, Page(s):164 - 167
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB)

    It is shown that when the standard Booth multiplication algorithm is extended to higher radix (>2) fixed-point multiplication, incorrect results are produced for some word sizes. A rule which modifies the algorithm to correct this problem is presented. The modification is defined for multipliers of any size, with any power of two radix.<> View full abstract»

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  • Fully differential optical interconnections for high-speed digital systems

    Publication Year: 1993, Page(s):151 - 163
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1553 KB)

    This work presents the design details and experimental results for a parallel optical link. The link is designed for connections within high-speed digital systems, specifically for board- and backplane-level interconnections. The link can contain as many fibers in parallel as technology permits. The unusual aspects of this interconnection system are that it is DC-coupled and uses fully differentia... View full abstract»

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  • Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums

    Publication Year: 1993, Page(s):138 - 150
    Cited by:  Papers (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1154 KB)

    The problem of concurrent error detection and fault tolerance is studied. These checksums of time-varying functions are possible because the function of a linear analog circuit can be represented mathematically by a set of matrices to which checksum codes can be applied. For the purpose of error detection, it is assumed that a fault can cause the value of a passive circuit component to deviate fro... View full abstract»

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  • Statistical timing analysis of combinational logic circuits

    Publication Year: 1993, Page(s):126 - 137
    Cited by:  Papers (53)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1263 KB)

    Efficient methods for computing an exact probability distribution of the delay of a combinational circuit, given probability distributions for the gate and wire delays, are developed. The derived distribution can give the probability that a combinational circuit will achieve a certain performance, across the possible range. This information can then be used to predict the expected performance of t... View full abstract»

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  • M*N Booth encoded multiplier generator using optimized Wallace trees

    Publication Year: 1993, Page(s):120 - 125
    Cited by:  Papers (79)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (503 KB)

    The architecture of a design method for an M-bit by N-bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N+or-M-1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N+or-M-1-bit adder is also presented.< View full abstract»

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  • Synthesis of timed asynchronous circuits

    Publication Year: 1993, Page(s):106 - 119
    Cited by:  Papers (63)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1550 KB)

    The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. Their timed circuits also tend to be more efficient, in both speed and area, compared with traditional asynchronous circuits. The synthesis procedure begins with a cyc... View full abstract»

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  • Cache sampling by sets

    Publication Year: 1993, Page(s):98 - 105
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (775 KB)

    An approach to workload sampling in which, instead of selection of memory references based on the time parameter, sample decisions are based on where the cache is accessed. More specifically, the sampling heuristics are focused on analysis for set-associative caches. The validity of the heuristics is supported with empirical data. Four sampling policies are discussed, and simulation results based ... View full abstract»

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  • Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips

    Publication Year: 1993, Page(s):88 - 97
    Cited by:  Papers (18)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (978 KB)

    A memory architecture with the capability of self-testing and self-repairing is presented. The contributions of this memory architecture are twofold. First, because it incorporates self-testing and self-repairing structures, the memory chip can perform tests, locate faults, and repair itself without any external assistance from either test engineers or test equipment. This will greatly improve the... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu